Silicon Labs Cp, Inc.

Keterex, Inc.

Danny Joe Allred

Kenneth Wilson Fernald

Donald E Alfano

Ka Yin Leung

Douglas S Piasecki

Douglas R Holberg

Paul Highley

Brian Caloway

Alvin Chuck Storvik

Alan Storvik

A reconfigurable processor includes a processor core for operating on a set of instructions to carry out predefined processes and includes a plurality of input/output pins in addition to a plurality of functional input/output blocks. These functional blocks allow the processing core to interface with the plurality of input/output pins, each of the functional input/output blocks having an associated and predetermined functionality. This functionality comprises the output as a function of the input, the function defined by the functionality. Each of the functional input/output blocks has a requirement for a defined number of the plurality of input/output pins wherein the total of the defined number for all of the plurality of functional input/output blocks exceeds the number of the plurality of input/output pins and wherein the processor core is interfaced with one of the input or output of each of the functional blocks. A reconfigurable interface selectively interfaces between the other of the input or output of the functional blocks and a select one or ones of the plurality of input/output pins, such that the processor core can be interfaced with the select one or ones of the input/output pins. The reconfigurable interface is operable to define how each of the plurality of input/output pins interfaces with the select ones of the plurality of functional blocks and the associated functionality in accordance with configuration information. A non-volatile memory is provided for storing information for use in association with the configuration information, such that the stored information can be altered.

Reconfigurable interface for coupling functional input/output blocks to limited number of I/O pins

An integrated circuit package includes a processing core for operating on a set of instructions to carry out predefined processes. A plurality of comparators perform compare operations within the integrated circuit package. At least one control register is associated with each of the plurality of comparators, and each of the plurality of comparators are software programmable to control a hysteresis of the comparators responsive to control bits established in the at least one control register of the comparator by the processing core. An amount of positive hysteresis is programmed via a first group of the control bits and an amount of negative hysteresis is programmed via a second group of the control bits.

Comparators in IC with programmably controlled positive / negative hysteresis level and open-drain / push-pull output coupled to crossbar switch or rising / falling edge interrupt generation

An ignition timing circuit is disclosed which provides variable fuel ignition timing as a function of the rotational speed of a small internal combustion engine. A measure of the rotational speed of an engine is generated from the shape of pulses generated by a sensor. A timing delay circuit converts this measure of the rotational engine speed into a fuel ignition trigger signal with a controlled delay relative to the engine's angular position. This trigger signal activates a switching device which in turn delivers energy to the engine's spark plug system. A significant benefit of the disclosed ignition timing circuit is its ability to be enclosed in a package which is size and pin-compatible with standard silicon controlled rectifiers.

Ignition timing circuit

An integrated circuit package includes a processing core and an internal oscillator. The processing core operates on a set of instructions to carry out predefined processes. The internal oscillator provides a system clock for the integrated circuit package. The internal oscillator has associated therewith an internal control register for controlling the operation of the internal oscillator responsive to control bits of the internal oscillator controlled by the processing core.

Integrated circuit package including programmable oscillators

A method for converting analog data to digital data includes operating an analog-to-digital data converter in a tracking mode to sample an input signal and in a convert mode to convert the sampled input signal after sampling to a digital signal. The analog-to-digital data converter is controlled with a controller to operate in different modes of operation by providing at least one step wherein the tracking mode of operation is controlled to initiate at a predetermined time to begin the sampling operation.

Analog-to-digital converter with low power track-and-hold mode

A reconfigurable processor system n an intergrated circuit includes a processor core that operates on a set of instructions to carry out predefined processes. A plurality of input/output pins are provided for interfacing with external signals. A reconfigurable interface interfaces between the processor core and the input/output pins through select ones of a plurality of functional blocks. The reconfigurable interface is operable to define how each of the plurality of input/output pins interfaces with the processor core an the functionality associated therewith. The functional blocks provide the interface of the processor core with the input/output pins.

Reconfigurable interface for coupling functional input/output blocks to limited number of i/o pins

A matrix of routing cells forming a cross-bar decoder (). Signal triplets () coupled to the cross-bar decoder () are assigned a priority. A register () provide outputs to the cross-bar decoder () to either activate or deactivate routing of the triplet signals () through the cross-bar decoder (). The routing cells () are arranged in a matrix of columns and rows, where the triplet signals are applied to the row routing cells () and are extracted at the column routing cells (). When a routing cell in a row is enabled to couple signals to an output, it disables all other lower priority routing cells in its column so that they cannot route signals to that output. Based on the automatic disabling of routing cells by others, the signals ripple through the cross-bar decoder () until all high priority I/O pins are used. The outputs of the cross-bar decoder () are coupled to respective I/O pins () by way of respective driver circuits ().

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Austin, TX, United States of America

Danny Joe Allred