David Sarnoff Research Center, Inc.

Sarnoff Corporation

Danny Chin

Joseph E Peters, Jr

Robert Bleidt

James Timothy Kaba

Herbert Hudson Taylor, Jr

Herbert H Taylor

James Timothy Christopher Kaba

Joseph Edward Peters, Jr

Sue-Kyoung Lee

Herbert H Taylor, Jr

A multiple user data storage, retrieval and distribution system containing a parallel processing computer system that forms a digital information server. The server contains a plurality of parallel processors each connected to a information storage device. The user data is stored in a distributed manner amongst the information storage devices. The distribution system dynamically allocates the users to the system based upon the user's requested operating mode. As such, during successive user service periods, all the users are supplied their requested data. The system also provides error detection and correction for the data requested by the users. Furthermore, additional data can be added to the information storage devices during each service period and select information storage devices can be recalibrated without affecting system operation. Even though the system allocates users dynamically such that the data is retrieved from the information storage devices in an arbitrary order, the system contains an output timing sequencer that generates output data in a predefined order no matter the order in which the data is retrieved from the information storage devices. The disclosed apparatus and method find applicability in video servers, medical imaging, special effects and animation and location based entertainment systems among other applications.

Method of striping data onto a storage array

Method of striping a data stream onto subsets of storage devices in a

A method for allocating multiple users to a multiple user data distribution system. More specifically, a data retrieval method for dynamically allocating multiple users to a plurality of parallel processors each connected to an information storage device in a multiple user distribution system. The method allocates each user to at least one processor. The allocated processor represents a slot within a service period. The service period comprises a plurality of slots such that within a given slot an allocated user accesses a subset of information storage devices to supply data to the user. The users are dynamically allocated to the slots in a service period such that the specific time at which each user is serviced and the subset of information storage devices that services them varies from service period to service period. However, each user is serviced during each service period. The allocation of the user within a service period is defined by the user's present mode of operation and next mode of operation, i.e., the mode the user will use in the next service period. Additionally, the method provides error detection and correction for the data retrieved from the information storage devices. Furthermore, the method enables new data to be added to the information storage devices during each service period and permits a select number of information storage devices, such as disk drives, to be recalibrated without impacting the operation of the system.

Method of allocating multiple users to a multiple user data distribution

An advanced massively parallel computer having a plurality of processor subsystems, where each processor subsystem is coupled to a secondary storage device (e.g., disk drive) through a secondary storage interface. The computer contains an input data bus for supplying data to the processor subsystem, an interprocessor communications bus for communicating data and instructions between processor subsystems, and an instruction bus for supplying instructions to the processor subsystems to facilitate data manipulation by each of the processor subsystems.

Advanced massively parallel computer with a secondary storage device

System for supplying streams of data to multiple users by distributing a

An apparatus and a method for combining the characteristics of both single instruction, multiple data stream (SIMD) and multiple instruction, multiple data stream (MIMD) computer architectures into a single parallel processing computer for performing multiple instruction stream processing. Such a parallel processing computer simultaneously performs both MIMD and SIMD operations on various processors within the computer. Additionally, at specified points during program execution, certain processors, i.e., a subset of all the processors, are synchronized. Once synchronized, the processors can exchange data. Moreover, the processors that do not take part in the synchronization continue executing instructions without interruption. The apparatus and method disclosed find applicability in video servers, medical imaging, special effects and animation and location based entertainment systems among other applications.

Parallel processing computer containing a multiple instruction stream

A processor within a parallel processing computer having a plurality of processors, where each processor is directly connected to a local storage memory. Each processor contains a principal processing element (PPE), a memory controller, and a multiplexor. The PPE executes a series of program instructions including local storage memory access instructions that cause the PPE to produce a local storage memory access request for accessing information within the local storage memory. The memory controller is connected to the PPE and a plurality of information resources of the parallel processing computer. This controller selectively routes local storage memory access requests from the information resources to an output port of the memory controller and generates an enable flag that is set to a first state when a selected one of the plurality of information resources can access the local storage memory and is set to a second state when the PPE is accessing the local storage such that access by the information resources is deferred until access by the PPE is complete. The multiplexor is connected to the PPE, the memory controller and the local storage memory. The multiplexor, operating in response to the enable flag, multiplexes the PPE access request with the selected information resource access requests such that access by the PPE to the local storage memory occurs substantially without time-delay interruption of the execution of program instructions by the PPE.

Method and apparatus for accessing local storage within a parallel

A parallel computing system comprising N blocks of processors, where N is an integer greater than 1. Each block of the N blocks of processors contains M processors, where M is an integer greater than 1. Each processor includes an arithmetic logic unit (ALU), a local memory and an input/output (I/O) interface. The computing system also contains a control means, connected to each of the M processors, for providing identical instructions to each of the M processors, and a host means, coupled to each of the control means within the N blocks of processors. The host means selectively organizes the control means of each of the N blocks of M processors into at least two groups of P blocks of M processors, P being an integer less than or equal to N. In operation, the host means causes the control means within each group of P blocks of M processors to provide each group of P blocks of M processors respectively different identical processor instructions. To facilitate communications amongst the processors, the parallel computing system includes an interprocessor communications channel that selectively interconnects the processors.

Advanced massively parallel computer using a field of the instruction to

A processor for use in a parallel computing system. The processor contains: a memory for storing operand values; an arithmetic logic unit (ALU) for performing arithmetic logic operations on operand values; a multiplier, separate from the ALU and coupled to the memory, for generating arithmetic products of a first operand value and a second operand values; and a match unit, separate from the ALU and coupled to the memory, for detecting matches between a predetermined bit pattern and a sequence of bits retrieved from the memory. The match unit also generates a count value indicating a number of detected matches between the predetermined bit pattern and subsequences of bits within the sequence of bits. The first operand value contains the bit pattern and the second operand contains the sequence of bits.

Apparatus for alternately activating a multiplier and a match unit

A routing process for a single-instruction-multiple-data (SIMD) multi-level hierarchical network of nodes, which are arranged in clusters and interconnected by dual, unidirectional channels, are used to send data packets including routing address information during a succession of routing cycles from transmitting ones to receiving ones of a large number of parallel processors (e.g., 4096 processors arranged in a hierarchy of 8 cabinets, each of which contains a cluster of 8 circuit boards, with each circuit board containing a cluster of 64 processors). Each of the nodes includes a storage buffer having a capacity equal to a given number which is one more than the total number of channels terminating at that node. This routing process guarantees prevention of deadlock between levels and buffer overflow, and offers high-speed, low-cost interprocessor communication for SIMD computers.

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Princeton Jct., NJ, United States of America

Danny Chin