Massachusetts Institute of Technology

Danna Rosenberg

William D Oliver

Rabindra N Das

Andrew J Kerman

Donna-Ruth Webb Yost

Mark A Gouker

Jonilyn L Yoder

Mollie Schwartz

Vladimir Bolkhovsky

Seth Lloyd

Michael F O'Keeffe

Wayne Woods

David J Hover

Cyrus Hirjibehedin

Iman Marvian Mashhad

Corey W Stull

Gabriel Samach

Morten Kjaergaard

Amy Greene

Thomas Hazard

Xhovalin Miloshi

Justin Mallek

Systems and methods for performing open-loop quantum error mitigation using quantum measurement emulations are provided. The open-loop quantum error mitigation methods do not require the performance of state readouts or state tomography, reducing hardware requirements and increasing overall computation speed. To perform a quantum measurement emulation, an error mitigation apparatus is configured to stochastically apply a quantum gate to a qubit or set of qubits during a quantum computational process. The stochastic application of the quantum gate projects the quantum state of the affected qubits onto an axis, reducing a trace distance between the quantum state and a desired quantum state.

Quantum measurement emulation error mitigation protocol for quantum computing

Qubit circuits having components formed deep in a substrate are described. The qubit circuits can be manufactured using existing integrated-circuit technologies. By forming components such as superconducting current loops, inductive, and/or capacitive components deep in the substrate, the footprint of the qubit circuit integrated within the substrate can be reduced. Additionally, coupling efficiency to and from the qubit can be improved and losses in the qubit circuit may be reduced.

Qubit circuits with deep, in-substrate components

A superconducting integrated circuit includes at least one superconducting resonator, including a substrate, a conductive layer disposed over a surface of the substrate with the conductive layer including at least one conductive material including a substantially low stress polycrystalline Titanium Nitride (TiN) material having an internal stress less than about two hundred fifty MPa (magnitude) such that the at least one superconducting resonator and/or qubit (hereafter called 'device') is provided as a substantially high quality factor, low loss superconducting device.

Superconducting integrated circuit

A multi-layer semiconductor structure includes a first semiconductor structure and a second semiconductor structure, with at least one of the first and second semiconductor structures provided as a superconducting semiconductor structure. The multi-layer semiconductor structure also includes one or more interconnect structures. Each of the interconnect structures is disposed between the first and second semiconductor structures and coupled to respective ones of interconnect pads provided on the first and second semiconductor structures. Additionally, each of the interconnect structures includes a plurality of interconnect sections. At least one of the interconnect sections includes at least one superconducting and/or a partially superconducting material.

Interconnect structures for assembly of semiconductor structures including superconducting integrated circuits

Described are concepts, systems, circuits and techniques related to shielded through via structures and methods for fabricating such shielded through via structures. The described shielded through via structures and techniques allow for assembly of multi-layer semiconductor structures including one or more superconducting semiconductor structures (or integrated circuits).

Shielded through via structures and methods for fabricating shielded through via structures

A cryogenic quantum bit package with multiple qubit circuits facilitates inter-qubit signal propagation using a multi-chip module (MCM). Multiple qubits are grouped within the package into one or more qubit integrated circuits (ICs). The qubit ICs themselves are electrically coupled to each other via a structure including a superconducting MCM and superconducting interconnects. Coupling of quantum electrical signals between a qubit and other qubits, a substrate, or the MCM uses a coupler circuit, such as a Josephson junction, capacitor, inductor, or resonator.

Qubit and coupler circuit structures and coupling techniques

A method of fabricating an interconnect structure includes providing a semiconductor structure and performing a first spin resist and bake cycle. The first spin resist and bake cycle includes applying a first predetermined amount of a resist material over one or more portions of the semiconductor structure and baking the semiconductor structure to form a first resist layer portion of a resist layer. The method also includes performing a next spin resist and bake cycle. The next spin resist and bake cycle includes applying a next predetermined amount of the resist material and baking the semiconductor structure to form a next resist layer portion of the resist layer. The method additionally includes depositing a conductive material in an opening formed in the resist layer and forming a conductive structure from the conductive material. An interconnect structure is also provided.

Interconnect structures and methods for fabricating interconnect structures

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Arlington, MA, United States of America

Danna Rosenberg