Cselt-centro Studi E Laboratori Telecomunicazioni S.p.a.

Danilo Galgani

Marco Gandini

Valter Bella

Andrea Finotello

A high speed digital signal transceiver in CMOS technology, in which the receiver has a clock signal extraction circuit, which is capable of self-aligning on incoming data with no spurious locks. Utilizing the PLL technique, the circuit generates a clock signal locked to the incoming signal utilizing a local oscillator, voltage-controlled by two feedback loops, a main one for frequency and phase corrections and a secondary one for phase correction. Moreover, original circuit solutions for the phase detectors and the low-pass filters are also envisaged.

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Turin, Italy

Danilo Galgani