Infineon Technologies North America Corp.

Danielle G Lemay

Venkat Mattela

Rod G Fleck

Heonchul Park

Roger D Arnold

Bruce Holmer

Balraj Singh

Andreas Grubert

An apparatus is described that comprises a data processing unit and at least one coprocessor. The data processing unit comprises a register file having registers, a memory, a plurality of execution units, a coprocessor interface for coupling the at least one coprocessor with the data processing unit, and a pipeline configuration for processing instructions having a fetch stage for fetching an instruction from the memory, a decode stage for decoding an operational code from the instruction, an execution stage for activating one of the execution units, and a write-back stage for God writing back from the execution unit. The data processing unit comprises read-and write-lines coupling the register file with the coprocessor for exchanging operands, at least one control line indicating that the coprocessor is busy, and a plurality of control lines from the decode stage for controlling the coprocessor which are operated upon detection of a coprocessor instruction. The coprocessor is using the registers from the register file during execution of the coprocessor instruction. The coprocessor comprises a decode unit for decoding the coprocessor instruction and a plurality of coprocessor execution units that share the decode unit, the decode unit selects one of the coprocessor execution units upon the coprocessor instruction, and the selected one of the coprocessor execution units performs the coprocessor instruction.

Data processing unit with interface for sharing registers by a processor and a coprocessor

An arrangement for shifting packed data is provided, in which packed data have multiple partial data each having n-byte, n being an integer greater or equal 1. The arrangement comprises: a shifter for shifting the packed data by a predetermined number of bits, a mask generator for generating a mask having multiple n-byte masks concatenated to the size of the packed data, and a logical unit for logically combining said mask with said shifted packed data to generate individually shifted partial data.

Method and apparatus for performing shift operations on packed data

A method for extracting n bits out of a data word stored in two concatenated registers each having a bit size of n bits starting with the m-th bit of the data register, m being smaller than n, comprises the following steps: The m significant bits of the first register are replaced with the m significant bits of the second register. Then, the result is stored in a register. Finally, the content of this register is rotated by m bits.

Method and apparatus for extracting data stored in concatenated registers

A method and apparatus for providing a program counter value within a central processing unit is described. A program counter value comprises n bits and has to be increased by one of a plurality of different fixed increment values. Therefore, an upper partial content of the current program counter value and its value incremented by 1 is provided. Also, a plurality of lower partial contents of the current program counter value incremented by one of the plurality of fixed increment values, respectively are provided, whereby a carry bit is provided. One of the plurality of incremented lower partial contents is selected depending on said respective carry bit. Upper and lower contents are then combined to form a plurality of new program counter values. Upon receiving of control information to select a final increment value one of said new program counter values will be selected.

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Sunnyvale, CA, United States of America

Danielle G Lemay