Stmicroelectronics Gmbh

Danielle A Thomas

Anthony M Chiu

Arnaud Yves Lepert

Frank R Bryant

Harry Michael Siegel

Bruno J Debeurre

Gilles E Thomas

Antonio A Do-Bento-Vieira

Antonio A Do Bento Vieira

Peter J Thoma

Alan H Kramer

Ming Fang

Giles E Thomas

In capacitive sensor circuits where physical contact is required and excess pressure may be inadvertently applied to the sensor surface, aluminum is not sufficiently hard to provide 'scratch' protection and may delaminate, causing circuit failure, even if passivation integrity remains intact. Because hard passivation layers alone provide insufficient scratch resistance, at least the capacitive electrodes and preferably all metallization levels within the sensor circuit in the region of the capacitive electrodes between the surface and the active regions of the substrate are formed of a conductive material having a hardness greater than that of aluminum, and at least as great as the lowest hardness for any interlevel dielectric or passivation material employed.

Scratch protection for direct contact sensors

Sensor cells are arranged in an array in an organic semiconductor layer. Row and column select circuitry addresses the cells of the array one cell at a time to determine the presence of an object, such as a fingerprint ridge or valley, contacting or proximate to a sensing surface above each cell. Control circuitry can be provided in a companion silicon chip or in a second layer of organic semiconductor material to communicate with the array and an associated system processor. The array of sensor cells can be fabricated using a flexible polymer substrate that is peeled off and disposed of after contacts have been patterned on the organic semiconductor layer. The organic semiconductor layer can be used with a superimposed reactive interface layer to detect specific chemical substances in a test medium.

Organic semiconductor sensor device

A system and method is disclosed for providing a redistribution metal layer in an integrated circuit. The redistribution metal layer is formed from the last metal layer in the integrated circuit during manufacture of the integrated circuit before final passivation is applied. The last metal layer provides sites for solder bump pads used in flip chip interconnection. The redistribution metal layer can be (1) a flat layer deposited over the next to last metal layer through an opening in a dielectric layer, or (2) deposited over an array of vias connected to the next to last metal layer. Space between the solder bump pads is deposited with narrower traces for connecting active circuit areas below. A final passivation layer is deposited to ensure product reliability.

Method for providing a redistribution metal layer in an integrated circuit

In capacitive sensor circuits where physical contact is required and excess pressure may be inadvertently applied to the sensor surface, aluminum is not sufficiently hard to provide 'scratch' protection and may delaminate, causing circuit failure, even if passivation integrity remains intact. Because hard passivation layers alone provide insufficient scratch resistance, at least the capacitive electrodes and preferably all metallization levels within the sensor circuit in the region of the capacitive electrodes between the surface and the active regions of the substrate are formed of a conductive material having a hardness greater than that of aluminum. The selected conductive material preferably has a hardness which is at least as great as the lowest hardness for any interlevel dielectric or passivation material employed. The selected conductive material is employed for each metallization level between the surface and the active regions, including contacts and vias, landing pads, interconnects, capacitive electrodes, and electrostatic discharge protection lines. Tungsten is a suitable conductive material, for which existing processes may be substituted in place of aluminum metallization processes.

System for providing a redistribution metal layer in an integrated circuit

A contact is formed within an active region of a substrate at the edge of a die, preferably within the first metallization level in the active region of the substrate. An opening having sloped sidewalls is then etched into the back side of the substrate, exposing a portion of the active region contact. An interconnect is formed on the opening sidewall to connect the active region contact with a die contact pad on the backside surface of the substrate. The active region contact preferably spans a boundary between two die, with the opening preferably etched across the boundary to permit inter-connects on opposing sidewalls of the opening to each contact the active region contact within different die, connecting the active region contact to die contact pads on different dice. The dice are then separated along the boundary, through the active region contact which becomes two separate active region contacts. By forming a shared contact opening spanning two dice, the backside contact is formed around the die edge and the backside surface area necessary for the contact opening is minimized. The backside contact allows direct placement of the integrated circuit die on contacts within the packaging, such as a ball grid array, eliminating the need for wire bonds. The need for a pad etch through passivation material overlying active devices on the front side of the die is also eliminated, and no mask levels are added for the devices formed on the front side.

Backside contact for touchchip

A large diameter glass wafer is pattern-etched to provide a plurality of elongated lens elements arranged side-by-side, the etching leaving small rods in place to keep the lens elements connected to the wafer during mirror processing. The etching provides curved surfaces for lenses and flat surfaces for mirrors. The mirrors are formed by selectively depositing reflective material on the flat surfaces. The reflective material may comprise an oxide, nitride, sulfide, or fluoride of a transition metal. The flat surfaces that define the mirrors are disposed at angles to the longitudinal dimension of each lens element. In use in an optical disc system, light from a laser diode is reflected by the mirrors and directed at an optical disc through a first lens. Light returns from the disc on a parallel path through a second lens, passes through the lens element, and is directed at a photodetector. The system may include an elongated base element attached to each lens element. Pattern-etching of a second glass wafer provides multiple base elements per wafer. Each base element may include an angled surface on which a reflective material is deposited to form a mirror for reflecting laser light during use in the system.

Method of making optical elements for an optical disc system

An integrated circuit includes a portion having at least one active circuit area. The integrated circuit also includes a redistribution metal layer fabricated at least partially during fabrication of the portion of the integrated circuit. A method for fabricating an integrated circuit includes fabricating a portion of the integrated circuit, where the portion includes at least one active circuit area. The method also includes fabricating a redistribution metal layer at least partially during fabrication of the portion of the integrated circuit.

Light from a laser diode is directed by mirrors on angled surfaces of an optical unit through a first lens at an optical disc. Light returns from the disc on a parallel path through a second lens and is directed at a photodetector. A semiconductor device controls the operation of the laser diode and receives signals form the photodetector for processing. The optical unit is formed from one or two glass elements cut from a larger glass wafer or wafers using photolithographic techniques. The mirrors are formed by thin films deposited on angled glass surfaces formed by selective plasma etching of the wafers. At least one mirror is partially reflective and is formed by depositing a thin film of titanium nitride.

Integrated optical unit for use with miniature optical discs

A photodetector is integrated on a single semiconductor chip with bipolar transistors including a high speed poly-emitter vertical NPN transistor. The photodetector includes a silicon nitride layer serving as an anti-reflective film. The silicon nitride layer and oxide layers on opposite sides thereof insulate edges of a polysilicon emitter from the underlying transistor regions, minimizing the parasitic capacitance between the NPN transistor's emitter and achieving a high frequency response. The method of manufacture is compatible with existing BiCMOS process technology, the silicon nitride layer of the anti-reflective film being formed over the photodetector as well as regions of the chip that include the vertical NPN transistor and other circuit elements.

Method of making an integrated photodetector in which a silicon nitride layer forms an anti-reflective film and part of multi-layer insulator within transistor structures

In capacitive sensor circuits where physical contact is required and excess pressure may be inadvertently applied to the sensor surface, aluminum is not sufficiently hard to provide &ldquo;scratch&rdquo; protection and may delaminate, causing circuit failure, even if passivation integrity remains intact. Because hard passivation layers alone provide insufficient scratch resistance, at least the capacitive electrodes and preferably all metallization levels within the sensor circuit in the region of the capacitive electrodes between the surface and the active regions of the substrate are formed of a conductive material having a hardness greater than that of aluminum. The selected conductive material preferably has a hardness which is at least as great as the lowest hardness for any interlevel dielectric or passivation material employed. The selected conductive material is employed for each metallization level between the surface and the active regions, including contacts and vias, landing pads, interconnects, capacitive electrodes, and electrostatic discharge protection lines. Tungsten is a suitable conductive material, for which existing processes may be substituted in place of aluminum metallization processes.

Metal taps for bus conductors are formed within an active layer, within one or more of the metallization levels, on the active side of a substrate in the area of a bus via. Alignment marks are formed in the same metallization level, in the same area. A slot is then blind etched from the backside of the substrate, exposing the metal taps and the alignment marks. The slot is etched, using an oxide or nitride hard mask, into the backside surface of the substrate with significantly sloped sidewalls, allowing metal to be deposited and patterned on the backside. An insulating layer and deposited metal on the backside surface of the substrate may require a blind etch to expose alignment marks, if any, but front-to-back alignment precision utilizing the exposed alignment marks may permit much smaller design rules for both the metal tabs and the backside interconnects formed from the metal layer. Backside contact pads may also be formed from the metal layer. The backside bus via slot may be etched in the body of a die, near a central region, or along the die boundary to form a shared backside bus via in which metal tabs on opposite sides of the slot connect to backside contacts on different dice after separation of the dice along the boundary. The backside bus is beneficial for sensor devices, leaving more room for sensor circuitry on the active side and simplifying packaging, for pad-limited designs, and for forming stackable integrated circuits.

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Dallas, TX, United States of America

Danielle A Thomas