Stmicroelectronics S.r.l.

Marvell International Limited

Invensense, Inc.

Daniele Ottini

Melchiorre Bruccoleri

Marco Pio Demicheli

Giacomino Bollati

Rinaldo Castello

Roberto Alini

Alessandro Venca

Francesco Rezzi

Omid Oliaei

Alessandro Savo

Paolo Rossi

Antonio Liscidini

Marco Sosio

Aurelio Pellegrini

Luca Celant

Davide Demicheli

Alberto Pirola

Paola Demartini

A circuit for a feedback system incorporates a gating mechanism to reduce flicker noise (e.g., a source for bias instability within a MEMS device) at a digital output. The gating mechanism generates a gating pulse with a delay period (e.g., a common, or fixed, delay including symmetrical rising and falling edge delays) that overrides internal delays (e.g., asymmetrical rising and falling edge delays) of a phase generator to prevent propagation delay (e.g., delay affected by jitter) from reaching subsequent feedback components (e.g., a digital-to-analog converter (DAC)) and contributing to the generation of flicker noise within the system.

Clocking scheme for reduced noise in continuous-time sigma-delta adcs preliminary class

Devices and methods capable of correcting for distortion are disclosed. For example, a method for compensating for non-idealities in a frequency-conversion circuit having a high-frequency input side separated from a baseband side by a passive mixer is presented. The method includes injecting a plurality of calibration signals in the baseband side to determine cross-talk between an In-phase (I) portion of the baseband side and a Quadrature (Q) portion of the baseband side to produce a first measurement &#x393;and a second measurement &#x393;, synthesizing a crosstalk compensation filter g(&#x3c9;) based on the first measurement &#x393;and the second measurement &#x393;, and applying the crosstalk compensation filter g(&#x3c9;) to an output of the frequency-conversion circuit.

Baseband filter calibration methods and systems

The present invention provides compensation for circuits. In one embodiment, a compensation circuit has a first terminal coupled to an output terminal of the circuit and a second terminal coupled to feed back the output voltage to an internal node. A damping circuit may also be coupled to the output terminal. The damping circuit adds a pole and a zero to the transfer function of the circuit. In one embodiment, the damping circuit modifies the effect of the output impedance of a load on the transfer function to increase the phase margin of the circuit such that the circuit remains stable over an increased range of output capacitor values.

Cascode compensation circuit and method for amplifier stability

A full-wave rectifier for monitoring the amplitude of a differential analog signal includes a differential Track&Hold stage controlled by a first differential logic timing signal tracking the differential analog input signal during a tracking phase that corresponds to a high logic stage of the first differential timing signal. This produces a differential output signal that is a replica of the input signal and the signal is stored during a successive storing phase that corresponds to a low logic state of the first differential timing signal. A first differential output amplifier includes inputs coupled to the output of the Track&Hold stage. A differential bistable circuit, controlled by a second differential logic timing signal, includes inputs coupled to the differential outputs of the first amplifier and produces a third differential logic control signal. A second multiplexed amplifier, controlled by the third differential control signal, includes inputs coupled to the output of the Track&Hold stage and produces a differential analog signal having an amplitude function corresponding to the amplitude of the differential input signal. A timing circuit receives at an input a differential logic synchronizing signal and generates the first differential timing signal of the Track&Hold stage and the second differential timing signal of the bistable circuit.

High frequency track and hold full-wave rectifier

A read and analog-to-digital data conversion channel includes an input circuit receiving an input data stream, and a time interleaved analog-to-digital converter connected to the input circuit. The time interleaved analog-to-digital converter includes a pair of analog-to-digital converters functioning in parallel and at half the clock frequency. A signal path through the time interleaved analog-to-digital converter is subdivided into two parallel paths through the pair of analog-to-digital converters. There is a first path for even bits and a second path for odd bits. A digital post-processing circuit is connected to the two parallel paths of the time interleaved analog-to-digital converter, and has an output providing a reconstructed data stream. At least one adjusting digital-to-analog converter is connected between the digital post-processing circuit and the input circuit for control thereof. The conversion channel further includes an offset circuit for compensating an offset in the pair of analog-to-digital converters in the time interleaved analog-to-digital converter. The offset circuit is controlled by the digital post-processing circuit, and includes first and second distinct offset compensating circuits independently controlled by the digital post-processing circuit.

Time interleaved digital signal processing in a read channel with reduced noise configuration

A phase locked loop is provided that includes a phase comparator, a charge pump circuit, a loop filter, and a voltage controlled oscillator. The charge pump circuit includes two symmetric branches, feedback paths, and circuit breaking switches. Each of the symmetric branches has a constant current generator and a pulsed current generator, with one terminal of the loop filter being connected to one of the symmetric branches and the other terminal of the loop filter being connected to the other of the symmetric branches. The feedback paths control the constant current generators based on voltages at the terminals of the loop filter, and each of the circuit breaking switches couple one of the pulsed current generators and the corresponding terminal of the loop filter. The pulsed current generators supply a first current whose amplitude is proportional to an amplitude of a second current supplied by the constant current generators through the duty cycle of the first current. In a preferred embodiment, the circuit breaking switches are controlled by phase error signals from the phase comparator. A method for controlling a charge pump circuit in a phase locked loop is also provided.

Phase locked loop and associated control method

A low pass filter with programmable equalization includes at least one biquadratic cell and a converter of the input voltage into a current, proportional to the derivative of the input voltage, that is injected on a node of the biquadratic cell to introduce two real and opposed zeros in the transfer function of the filter. The low pass filter includes two structurally similar circuits functionally connected in cascade. Each circuit includes a biquadratic cell and an input stage having two outputs injecting, through a first current output, the current to an input capacitor of the respective biquadratic cell, by a direct coupling in a first of the two circuits and in an inverted manner in the second of the two circuits. A second voltage output is coupled to an input of the respective biquadratic cell.

Analog equalization low pass filter structure

A flash analog-to-digital converter includes a bank of comparators with a differential output, generating a thermometric code, and a bank of three-input logic NOR gates. The converter has enhanced immunity to noise and reduced imprecisions by providing for a passive interface including a plurality of voltage dividers each connected between the noninverted output of a respective comparator and the inverted output of the comparator of higher order of the bank. A corresponding logic NOR gate of the bank has a first input coupled to the inverted output of the respective comparator, a second input coupled to the noninverted output of the comparator of higher order and a third input coupled to an intermediate node of the voltage divider.

Analog-to-digital flash converter for generating a thermometric digital code

A differential decoder has a wide output dynamic range and reduced area consumption. The decoder includes a plurality of inputs which are correlated to a plurality of output lines. The output lines are driven by respective NPN type bipolar transistors which are connected to the output lines by their emitters while the input signals are fed to their bases. The decoder also includes a plurality of additional output lines which are complementary to the output lines and another plurality of NPN type bipolar transistors which are suitable to drive the additional output lines. The additional bipolar transistors are connected to the additional output lines through their emitter terminals, and are connected to the base and collector terminals of the bipolar transistors that drive the output lines, through their base and collector terminals.

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Pavia, Italy

Daniele Ottini