Telefonaktiebolaget Lm Ericsson (Publ)

Daniele Mastantuono

Sven Erik Mattisson

Lars Sundström

Roland Strandberg

Mattias Palm

Pietro Andreani

Fenghao Mu

Sunny Sharma

An ADC includes a plurality of sub ADCs configured to operate in a time-interleaved manner and a sampling circuit configured to receive an analog input signal of the ADC, wherein the sampling circuit is common to all sub ADCs. The ADC includes a test signal generation circuit configured to generate a test signal for calibration of the ADC. The sampling circuit has a first input configured to receive the analog input signal and a second input configured to receive the test signal. The sampling circuit includes an amplifier circuit and a first feedback switch connected between an output of the amplifier circuit and an input of the amplifier circuit. The first feedback switch is configured to be closed during a first clock phase and open during a second clock phase, which is non-overlapping with the first clock phase.

Time-interleaved analog-to-digital converter

A multipath bootstrapped sampling circuit includes a sampling capacitor, a sampling transistor interposed between the sampling capacitor and the analog input signal voltage, two bootstrap capacitors, and a bootstrap switching network periodically transitioning between a holding phase and a tracking phase. The bootstrap switching network includes a primary bootstrap path that drives only one load: the gate terminal of the sampling transistor. One or more auxiliary bootstrap paths drive other transistors in the bootstrap switching network. This absolutely minimizes the parasitic capacitance due to fan-out on the primary bootstrap path. Additionally, the provision of two (or more) bootstrap capacitors allows bulk terminals of transistors on the primary bootstrap path to be connected to an auxiliary bootstrap path, further reducing parasitic capacitance on the primary bootstrap path. Additional auxiliary bootstrap paths may be added, providing the opportunity to optimize each clock driver to a specific driven transistor. Additional bootstrap capacitors may be added, to distribute the capacitance among auxiliary bootstrap paths. The reduction in parasitic capacitance at the sampling transistor enhances its linearity, and hence accuracy, at very high frequencies.

Multiple paths bootstrap configuration for sample and hold circuit

The present disclosure generally relates to the field of receiver structures in radio communication systems and more specifically to passive mixers in the receiver structure and to a technique for converting a first signal having a first frequency into a second signal having a second frequency by using a third signal having a third frequency. A passive mixer for converting a first signal having a first frequency into a second signal having a second frequency by using a third signal having a third frequency comprises a cancellation component for generating a first cancellation signal for cancelling second order intermodulation components by superimposing the first signal weighted by a cancellation value on the third signal; and a mixing component having a first terminal for receiving the first signal, a second terminal for outputting the second signal, and a third terminal for receiving the first cancellation signal, wherein the mixing component is adapted to provide the second signal as output at the second terminal by mixing the first signal provided as input at the first terminal and the first cancellation signal provided as input at the third terminal.

Passive mixer with reduced second order intermodulation

A pipelined ADC includes a first sub ADC and a second sub ADC. The second sub ADC is configured to receive, as an input, an analog residue generated by the first sub ADC. The first sub ADC is configured to operate in a first conversion phase, generating a digital output of the first sub ADC, and a second conversion phase, generating the analog residue. The first sub ADC includes a reference-voltage generator circuit configured to generate a reference voltage of the first sub ADC and having a first mode of operation and a second mode of operation, in which the noise power of the reference voltage is less than in the first mode of operation. The reference-voltage generator circuit is configured to operate in its first mode of operation in the first conversion phase and in its second mode of operation in the second conversion phase.

Pipelined analog-to-digital converter

The present disclosure generally relates to the field of receiver structures in radio communication systems and more specifically to passive mixers in the receiver structure and to a technique for converting a first signal having a first frequency into a second signal having a second frequency by using a third signal having a third frequency. A passive mixer for converting a first signal having a first frequency into a second signal having a second frequency by using a third signal having a third frequency comprises a cancellation componentfor generating a first cancellation signal for cancelling second order intermodulation components by superimposing the first signal weighted by a cancellation value on the third signal; and a mixing componenthaving a first terminalfor receiving the first signal, a second terminalfor outputting the second signal, and a third terminalfor receiving the first cancellation signal, wherein the mixing componentis adapted to provide the second signal as output at the second terminalby mixing the first signal provided as input at the first terminaland the first cancellation signal provided as input at the third terminal

Systems and methods of noise suppression by an amplifier are presented. In one exemplary embodiment, an amplifier comprises first and fourth transistors configured as a first differential pair of transistors in a common-gate configuration, and second and third transistors configured as a second differential pair of transistors in a common-source configuration. The first and fourth transistors are operative to receive, from a differential input, by a source of each first and fourth transistor, a differential input signal. Further, a drain of each first and fourth transistor is coupled to respective first and second outputs configured as a differential output. The second and third transistors are operative to output, from a drain of each second and third transistor, to the respective second and first outputs, a differential output signal. Further, a gate of each second and third transistor is coupled to the respective first and second inputs.

Amplifier adapted for noise suppression

A radio frequency receiver having a plurality of parallel receiving paths, wherein each path can receive a radio frequency signal in one of a plurality of radio frequency bands and amplify the received signal in a low noise amplifier. The amplified signals from the plurality of parallel paths are combined to one combined radio frequency signal in a common summation node and down-converted to a lower frequency signal in a mixer circuit. Each low noise amplifier comprises a low noise transconductance circuit providing a current signal to drive the common summation node, and an automatic gain control circuit in each path compensates for variations in signal strength independently of signal strengths of signals received by the other receiving paths. The receiver is suitable for simultaneous multiple band reception, where received signal strength can vary between the frequency bands.

Receiving a plurality of radio frequency bands

A receiver front end arrangement comprises a radio frequency signal input suitable to be connected to an antenna arrangement, a filter bank of non-overlapping band filters associated with respective band for the multi-band reception, a signal conditioning arrangement connected to the filter bank, and a low-noise amplifier arrangement connected to the signal conditioning arrangement. The low-noise amplifier arrangement comprises a path for each band of bands of the multi-band reception. For each path associated with a band for the multi-band reception the low-noise amplifier arrangement comprises a low-noise amplifier. The respective low-noise amplifier has band pass characteristics, or has a band filter connected where the band filter output has a direct connection to the input of the low-noise amplifier, corresponding to a band of the multi-band reception, respectively. The receiver front end arrangement further comprises a combiner structure arranged to combine the outputs of the respective low-noise amplifier of the paths of the low-noise amplifier arrangement. The signals at the output of the combiner structure have the same frequencies as the corresponding signals at the radio signal input. The signal conditioning arrangement is arranged to condition signals for respective path of the low-noise amplifier arrangement. A multi-band receiver comprising the receiver front end arrangement, and a base station comprising the multi-band receiver are also disclosed.

Receiver front end arrangement, multi-band receiver and base station

An amplifier () adapted for noise suppression comprises a first input () for receiving a first input signal and a second input () for receiving a second input signal, the first and second input signals constituting a differential pair. A first output () delivers a first output signal and a second output () delivers a second output signal, the first and second output signals constituting a differential pair. A first transistor (M) has a first drain () coupled to the first output () such that all signal current, except parasitic losses, flowing through the first drain () flows through the first output (), and the first transistor (M) further having a first source () coupled to the first input (). A second transistor (M) has a second gate () coupled to the first input (), a second drain () coupled to the second output () such that all signal current, except parasitic losses, flowing through the second drain () flows through the second output (), and the second transistor (M) further having a second source () coupled to a first voltage rail (). A third transistor (M) has a third gate () coupled to the second input (), a third drain () coupled to the first output () such that all signal current, except parasitic losses, flowing through the third drain () flows through the first output (), and the third transistor (M) further having a third source () coupled to the first voltage rail (). A fourth transistor (M) has a fourth drain () coupled to the second output () such that all signal current, except parasitic losses, flowing through the fourth drain () flows through the second output (), and the fourth transistor (M) further having a fourth source () coupled to the second input (). A first load (Z) is coupled between the first output () and a second voltage rail (). A second load (Z) is coupled between the second output () and the second voltage rail (). A first inductive element (L) is coupled between the first input () and a third voltage rail (), and a second inductive element (L) is coupled between the second input () and the third voltage rail (). Transconductance of the first transistor (M) is substantially equal to transconductance of the fourth transistor (M), within &#xb1;5%, and transconductance of the second transistor (M) is substantially equal to transconductance of the third transistor (M), within &#xb1;5%.

A radio frequency receiver comprises a plurality of parallel receiving paths, wherein each path can receive a radio frequency signal in one of a plurality of radio frequency bands and amplify the received signal in a low noise amplifier. The amplified signals from the plurality of parallel paths are combined to one combined radio frequency signal in a common summation node and down-converted to a lower frequency signal in a mixer circuit. Each low noise amplifier comprises a low noise transconductance circuit providing a current signal to drive the common summation node, and an automatic gain control circuit in each path compensates for variations in signal strength independently of signal strengths of signals received by the other receiving paths. The receiver is suitable for simultaneous multiple band reception, where received signal strength can vary between the frequency bands.

High bandwidth amplifier

In a passive mixer, switches and a capacitance are shared between bootstrapped mixing transistors, reducing the number of components required as compared to prior art bootstrap designs. Shared bootstrap circuits operate in an interleaved fashion between I and Q mixer circuits, at twice the LO frequency. That is, the shared bootstrap circuits in each I mixer circuit charge their capacitors in a first half-period of a clock, and connect the shared capacitor to the gate of an enabled mixing transistor in the second half-period. The shared bootstrap circuits in the Q mixer circuit charge their capacitors in the second half-period, and connect the shared capacitor to the gate of an enabled mixing transistor in the first half-period. One of two mixing transistors connected to each shared bootstrap circuit is alternately enabled during the clock signal half-periods that the shared bootstrap circuit is not charging its capacitor.

Low power and area bootstrapped passive mixer with shared capacitances

In a time-interleaved Analog to Digital Converter, circuit components and capacitances may be shared among a plurality of sample and hold circuits in each of two sets. The two shared circuits alternate, on different half-periods of a master clock signal, between charging a capacitance and sampling an input in an overlapping manner such that one is charging while the other is sampling. One sample and hold circuit is activated during each successive half-period (following a charging half-period) by independent, sequential, non-overlapping clocking signals. To improve SNDR, at least one switch is bootstrapped by driving its gate terminal with the voltage of a capacitor configured between the gate and the input signal. By sharing at least some components among multiple sample and hold circuits, the number of gates driven by clock signals is reduced, reducing clock distribution and calibration complexity, and the circuit area is reduced.

Growing community of inventors

Lund, Sweden

Daniele Mastantuono