Imec

Katholieke Universiteit Leuven, Ku Leuven R&d

Daniele Leonelli

Anne S Verhulst

Rita Rooyackers

Marc Marcel Heyns

Roger Loo

Wim Dehaene

Cedric Huyghebaert

Stefan De Gendt

Anne Vandooren

A tunnel transistor is provided including a drain, a source and at least a first gate for controlling current between the drain and the source, wherein the first sides of respectively the first and the second gate dielectric material are positioned substantially along and substantially contact respectively the first and the second semiconductor part.

Tunnel transistor, logical gate including the transistor, static random-access memory using the logical gate and method for making such a tunnel transistor

The present disclosure provides a method for manufacturing at least one nanowire Tunnel Field Effect Transistor (TFET) semiconductor device. The method comprises providing a stack comprising a layer of channel material with on top thereof a layer of sacrificial material, removing material from the stack so as to form at least one nanowire from the layer of channel material and the layer of sacrificial material, and replacing the sacrificial material in the at least one nanowire by heterojunction material. A method according to embodiments of the present disclosure is advantageous as it enables easy manufacturing of complementary TFETs.

Method of manufacturing a complementary nanowire tunnel field effect transistor semiconductor device

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Leuven, Belgium

Daniele Leonelli