Micron Technology Incorporated

Politecnico Di Milano

Stmicroelectronics S.r.l.

Daniele Ielmini

Fabio Pellizzer

Agostino Pirovano

Paolo Fantini

Nicola Ciocchini

Andrea Redaelli

Angelo Visconti

Mattia Boniardi

Mauro Bonanomi

Simone Balatti

Stefano Ambrogio

Zhongqiang Wang

Zhong Sun

Giacomo Pedretti

Alessandro Spinelli

The disclosed technology generally relates to memory apparatuses and methods of operating the same, and more particularly to a memory device having a controller configured to cause a write operation to be performed on a variable resistance memory cell, which includes application of two successive access pulses having opposite polarities, and methods of using the same.

Apparatuses and methods for accessing variable resistance memory device

The invention relates to a device for generating random numbers, comprising a pair of memristors. The pair of memristors comprises a first and a second memristor, each memristor of the pair in turn comprises a top electrode, a bottom electrode and an intermediate layer adapted to switch resistance in response to predetermined voltage values applied between the top electrode and the bottom electrode. Each memristor is operatively connected to an output terminal by means of its bottom electrode. A control logic is connected to the memristors for applying suitable voltages necessary to determine a change of resistance in at least one memristor of the pair.

Device and method for generating random numbers

A synaptic circuit performing spike-timing dependent plasticity STDP interposed between a pre-synaptic neuron and a post-synapse neuron includes a memristor having a variable resistance value configured to receive a first signal from the pre-synaptic neuron. The circuit has an intermediate unit connected in series with the memristor for receiving a second signal from the pre-synaptic neuron and provides an output signal to the post-synaptic neuron. The intermediate unit receives a retroaction signal generated from the post-synaptic neuron and the memristor modifies the resistance value based on a delay between two at least partially overlapped input pulses, a spike event of the first signal and a pulse of the retroaction signal, in order to induct a potentiated state STP or a depressed state STD at the memristor. An electronic neuromorphic system having synaptic circuits and a method of performing spike timing dependent plasticity STDP by a synaptic circuit are also provided.

Electronic neuromorphic system, synaptic circuit with resistive switching memory and method of performing spike-timing dependent plasticity

Subject matter disclosed herein relates to techniques involving a structural relaxation (SR) phenomenon for increasing resistance of a Reset state of phase change memory.

Modified reset state for enhanced read margin of phase change memory

A potential supplied to selected cells in a Phase Change Memory (PCM) is reversed in polarity following a program operation to suppress a recovery time and provide device stabilization for a read operation.

Reversing a potential polarity for reading phase-change cells to shorten a recovery delay after programming

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Bergamo, Italy

Daniele Ielmini