Stmicroelectronics S.r.l.

Daniela Peschiaroli

Alfonso Maurelli

Elisabetta Palumbo

Fausto Piazza

Emilio Camerlenghi

Nicola Zatelli

Paola Zabberoni

Barbara Crivelli

A method for sealing electronic devices formed on a semiconductor substrate includes forming at least one first conductive layer on a first portion of the semiconductor substrate for defining electronic devices, and forming a second conductive layer on a second portion of semiconductor substrate for also defining electronic devices. First regions are formed in the at least one first conductive layer for defining electronic devices, and a first sealing layer is formed on the whole semiconductor substrate to seal the first regions. Second regions are formed in the second conductive layer for defining electronic devices, and a second sealing layer is formed on the whole semiconductor substrate to seal the second regions.

Sealing method for electronic devices formed on a common semiconductor substrate and corresponding circuit structure

A method for manufacturing an integrated circuit having a memory device and a logic circuit includes forming a plurality of first transistors in a first portion of a semiconductor substrate, a plurality of second transistors in a second portion of the semiconductor substrate, and a plurality of memory cells in a third portion of the semiconductor substrate. A matrix mask used for selectively removing a dielectric layer from the first and third portions of the semiconductor substrate allows dielectric to remain on a floating gate of the plurality of memory cells and on the gate electrodes of the plurality of first transistors. A control gate is then formed on the floating gate, which is separated by the dielectric. Portions of the gate electrodes for the plurality of first transistors are left free so that contact is made with the transistors.

Method of manufacturing an integrated circuit, for integrating an electrically programmable, non-volatile memory and high-performance logic circuitry in the same semiconductor chip

Method of manufacturing an electrically programmable, non-volatile memory and high-performance logic circuitry in the same semiconductor chip

Active areas and body regions are formed in a substrate for forming low voltage MOS transistors, high voltage MOS transistors, and EPROM cells. A thermal oxide layer is formed on the substrate, and a first polycrystalline silicon layer is formed on the thermal oxide layer. The polycrystalline silicon layer is selectively removed to form the floating gate electrodes of the EPROM cells, and the source and drain regions of the EPROM cells are also formed. The active areas for the high voltage MOS transistors are exposed, and a layer of high temperature oxide is formed and nitrided. The active area for the low voltage MOS transistors are exposed, and a layer of thermal oxide is formed on the exposed areas. A second polycrystalline silicon layer is deposited, which is then selectively removed to form the gate electrodes of the low voltage and high voltage MOS transistors, and the control gate electrodes of the EPROM cells.

Process for the fabrication of an integrated circuit comprising MOS transistors for low voltage, EPROM cells and MOS transistors for high voltage

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Milan, Italy

Daniela Peschiaroli