Qualcomm Incorporated

Applied Micro Circuits Corporation

Daniel Yingling

Keith Alan Bowman

Dipti Ranjan Pal

Francois Ibrahim Atallah

Hoan Huu Nguyen

Jihoon Jeong

Yu Pu

Robert J Vachon

Robert Oden

Yimai Peng

Joseph Rash

Herbert Rivera Sanchez

An apparatus, including: a first flip-flop including a scan input configured to receive a scan signal, a clock input configured to receive a first clock signal of a first clock domain; a latch including an input coupled to an output of the first flip-flop, a clock input configured to receive a control signal; and a second flip-flop including a scan input coupled to an output of the latch, a clock input configured to receive a second clock signal of a second clock domain, and an output configured to generate the scan signal, wherein at least one of the first or second flip-flop comprises a first dual-edge-triggered (DET) flip-flop.

Lock-up latch for dual-edge-triggered flip-flops

An apparatus, including: a clock gating circuit (CGC), including: a clock gating device configured to selectively gate/pass a selected clock signal based on an enable signal to generate an output clock signal; and a clock selection circuit configured to select a non-complementary clock signal or a complementary clock signal to generate the selected clock signal based on the output clock signal and the non-complementary clock signal or the complementary clock signal.

Clock gating circuit for dual-edge-triggered flip-flops

Aspects of the present disclosure related to a method of duty-cycle distortion compensation in a system including a clock generator configured to generate a clock signal. The method includes measuring one or more parameters of the clock signal, determining a duty-cycle adjustment based on the measured one or more parameters, and adjusting a duty cycle of the clock signal based on the determined duty-cycle adjustment.

Adaptive clock duty-cycle controller

Aspects of the present disclosure related to a method of phase extension using a delay circuit including delay devices coupled in series. The method includes receiving a clock signal, generating multiple delayed versions of the clock signal, wherein each of the delayed versions of the clock signal is delayed by a different number of the delay devices, and combining high phases or low phases of the delayed versions of the clock signal to obtain a combined clock signal.

A method of measuring a clock signal includes launching an edge of a timing signal on a first edge of the clock signal, outputting an edge of a capture signal on a second edge of the clock signal, receiving the edge of the timing signal and the edge of the capture signal at a time-to-digital converter (TDC), and measuring a time delay using the TDC, wherein the time delay is between a time the edge of the timing signal is received at the TDC and a time the edge of the capture signal is received at the TDC.

A dual-mode memory is provided that includes a self-timed clock circuit for asserting a sense enable signal for a sense amplifier. In a low-bandwidth read mode, the self-timed clock circuit asserts the sense enable signal only once during a memory clock cycle. The sense amplifier then senses only a single bit from a group of multiplexed columns. In a high-bandwidth read mode, the self-timed clock circuit successively asserts the sense enable signal so that the sense amplifier successively senses bits from the multiplexed columns.

Dual-mode high-bandwidth SRAM with self-timed clock circuit

A system and method are provided for tracking connections in a network bundle including a plurality of network links. The method comprises: receiving packet fragments in a plurality of sampling rounds; for a current sampling round, recording which links have supplied a packet fragment; and, advancing a record of the received packet fragments in response a packet fragment on each link. Typically, the packet fragments are received with a corresponding first plurality of sequence numbers. Then, the lowest sequence number in the completed current sampling round is recorded. Some aspects of the method additionally comprise: for the current sampling round, establishing a flag register with a flag for each link; establishing a next lowest sequence number (Mn) register; and, establishing a current lowest sequence number (Mc) register. Then, a flag register flag is toggled in response to receiving a packet fragment on a corresponding link.

System and method for tracking multilink packet information

A system and method are provided for initiating the reassembly of received packet fragments in a multilink communication network. The method comprises: receiving packet fragments with corresponding sequence numbers; counting the number of fragments received since the initiation of a pervious packet fragment reassembly; and, initiating packet fragment reassembly in response to the fragment count. Some aspects of the method further comprise: establishing a threshold; and, comparing the fragment count to the threshold. Then, initiating packet fragment reassembly includes initiating packet fragment reassembly when the fragment count equals the threshold. Other aspects of the method comprise tracking a RFC-1990 M value. Then, establishing a threshold includes establishing a WITH_M_UPDATE threshold. Initiating packet fragment reassembly includes initiating packet fragment reassembly in response to the combination of: the fragment count equaling the WITH_M_UPDATE threshold; and, the M value changing since the initiation of a pervious packet fragment reassembly.

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Apex, NC, United States of America

Daniel Yingling