Silicon Graphics, Incorporated

Daniel Yau

James E Tornes

Steven C Miller

Kianoosh Naghshineh

Desmond W Young

Jeannine Marie Smith

Jamie Riotto

Greg Chesson

Yuh-wen Lin

In-whan Choi

Jeffery M Smith

Karim M Abdalla

A novel packet switched routing architecture for establishing multiple, concurrent communications between a plurality of devices. Any number of devices are coupled to a central packet switched router via links. Due to the nature of these tightly coupled links, high data rates can be achieved between devices and the packet switched router with minimal pins. Any device can communicate to any other device via the packet switched router. The packet switched router has the capability of establishing multiple communication paths at the same time. Hence, multiple communications can occur simultaneously, thereby significantly increasing the overall system bandwidth.

Packet switched router architecture for providing multiple simultaneous communications

A cache for AGP based computer systems is provided. The graphics cache is included as part of a memory bridge between a processor, a system memory and a graphics processor. A cache controller within the memory bridge detects requests by the processor to store graphics data in the system memory. The cache controller stores the data for these requests in the graphics cache and in the system memory. The cache controller searches the graphics cache each time it receives a request from the graphics controller. If the a cache hit occurs, the cache controller returns the data stored in the graphics cache. Otherwise the request is performed using the system memory. In this way the graphics cache reduces the traffic between the system memory and the memory bridge, overcoming an important performance bottleneck for many graphics systems.

Enhanced graphics cache memory

A method and apparatus for controlling the flow of information (e.g., graphics primitives, display data, etc.) to an input/output unit within a computer controlled graphics system. The system includes a processor having a first-in-first-out (FIFO) buffer, a separate input/output unit with its FIFO buffer, and a number of intermediate devices (with FIFO buffers) coupled between the input/output unit and the processor for moving input/output data from the processor to the input/output unit. Mechanisms are placed within an intermediate device, very close to the processor, which maintain an accounting of the number of input/output data sent to the input/output unit, but not yet cleared from the input/output unit's buffer. These mechanisms regulate data flow to the input/output unit. By placing these mechanisms close to the processor, rather than within the input/output unit, the system allows a larger portion of the input/output unit's buffer to be utilized for storing input/output data before a processor suspend or interrupt is required. This leads to increased input/output data throughput between the processor and the input/output unit by reducing processor interrupts. The system also includes an efficiently invoked timer mechanism for temporarily suspending the processor from transmitting stores to the input/output unit when the input/output unit and/or the intermediate devices are congested. The processor is not interrupted by an interrupt request until after the timer mechanism times out, allowing the system an opportunity to clear its congestion before a lengthily invoked interrupt is required.

Upstream situated apparatus and method within a computer system for

A data stream processing unit comprises a CPU which comprises an ALU, a shift/extract unit, timers, a scheduler, an event system, a plurality of sets of general purpose registers, a plurality of sets of special purpose registers, masquerade registers, pipeline controller, a memory controller and a pair of internal buses. The multiple sets of general and special purpose registers improves the speed of the CPU in switching between environments. The pipeline controller, the scheduler, the events system, and the masquerade registers facilitate the implementation and execution of the methods of the present invention such as efficient thread scheduling, branch delays, elimination of delay slots after stores that provide further increases in the performance and bandwidth.

Central processing unit for processing a plurality of threads using

A method and circuit providing for an accurate sampling of data on a high speed bus in a computer system. Utilizing a single clock source, functional units that are capable of supporting two clock input sources, and a routing technique that provides for a receiving unit to be clocked prior to a transmitting unit, data transfer can occur reliably and economically on a high speed bus. Synchronization within a particular unit is accomplished by providing serial edge-triggered registers that are triggered by the respective clock inputs.

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Los Altos, CA, United States of America

Daniel Yau