Brocade Communications Systems, Inc.

Xilinx, Inc.

Avago Technologies International Sales Pte. Limited

Brocade Communication Systems LLC

Daniel Y Chung

Dennis Hideo Makishima

Robert O Conn

Robert W Wells

Robert D Patrie

Howard Green

Brian Forbes

Glenn Wenig

Howard Lynn Johnson

David L Ferguson

Gil A Speyer

Dave Peterson

Feejen Liao

Steven P Young

Subhojit Roy

Grant Michael Erickson

Tim Tuan

Matthew H Klein

John K Jennings

Christopher H Kingsley

Badrinath Kollu

Nui Chong

Ronald L Cline

Cheang-Whang Chang

Daniel Ji Yong Park Chung

Vincent W Guan

Jesse Willeke

Shahe Hagop Krakirian

Ping-Chin Yeh

Richard A Walter

Naveen Maveli

L Vincent M Isip

Cirillo Lino Costantino

Andy DeBaets

Annie Wang

Subbaro Arumilli

Stephen D Elstad

Mohan Babu Raju

Rhesa Nathanael

Cheng-Whang Chang

A network where FC and Ethernet storage traffic share the network. The network extends FC SAN storage attributes to Ethernet storage devices. The network is preferably formed of FC switches, so each edge switch acts as an FCoE FCF, with internal communications done using FC. IP packets are encapsulated in FC packets for transport. Preferably, either each outward facing switch port can be configured as an Ethernet or FC port, so devices can be connected as desired. Ethernet addresses of IP devices are discovered based on ARP requests and lookup misses. Once an ARP request is trapped, the source device's information is added to a local database and distributed within the network. If the destination device is not known, a network-specific fabric protocol is used to propagate the ARP request to the other switches. An ARP response is processed similarly to update the local database and to distribute the update.

Address resolution protocol operation in a fibre channel fabric

In an example implementation, an integrated circuit (IC) includes: a plurality of transistors disposed in a plurality of locations on a die of the IC; conductors coupled to terminals of each of the plurality of transistors; a digital-to-analog converter (DAC), coupled to the conductors, to drive voltage signals to the plurality of transistors in response to a digital input; and an analog-to-digital converter (ADC), coupled to at least a portion of the conductors, to generate samples in response to current signals induced in the plurality of transistors in response to the voltage signals, the samples being indicative of at least one electrostatic characteristic for the plurality of transistors.

In-die transistor characterization in an IC

In a Fiber Channel SAN and its included routers, each router contains only the LSAN zones that contain devices attached to edge fabrics which are connected to the router. LSAN zone entries include the fabric ID (FID) of each device in addition to the WWN. When a router obtains a new zone database for a newly connected or changed fabric, the router scans the LSAN zone entries for fabric IDs matching a fabric connected to the router and stores those entries. All other LSAN zone entries are not stored. In this manner the size of the relevant tables are reduced, which allows for greater expansion of the SAN as a whole.

Increased fabric scalability by location based zoning

Is in a Fibre Channel storage area network (SAN) and its included routers, the routers are placed in groups or pods. Each router only contains router port and fabric access data for routers in the same group or pod. In this manner the size of the relevant tables are reduced, which allows for greater expansion of the SAN as a whole. Each router may be programmed by an administrator with a pod value, indicating the pod containing the router. This value may be provided to the Name Server during router registration and may be requested from the Name Server when developing the router's inter-fabric router (IFR) topology or the pod value can be exchanged in the IF_ILS_HLO messages. Router port database information is only stored from routers in the same pod or provided to routers in the same pod, thus reducing the entries in the router port database.

Increased fabric scalability by designating router groups

An FCoE VN_Port virtualizer where VF_Ports are used to connect downstream to host and target VN_Ports and a VN_Port is used to connect upstream to further FCoE VN_Port virtualizers or to an FCF. An alternate embodiment uses an Ethernet Fabric for an additional purpose. The Ethernet Fabric devices all act as FCoE VN_Port virtualizers, so that the Ethernet Fabric itself is considered a virtual FCoE VN_Port virtualizer.

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Ethernet Fabric devices all act as FCoE to FC gateways, so that the Ethernet Fabric itself is considered a virtual FCoE to FC gateway. Further, the Ethernet Fabric allows direct routing of FCoE packets from one FCoE device coupled to the Ethernet Fabric to another FCoE device coupled to the Ethernet Fabric.

A method and circuit for device specific configuration of an operating voltage is provided. A circuit design is analyzed to determine a maximum gate-level delay for the circuit design. A minimum voltage value corresponding to the maximum gate-level delay is determined along with a default voltage value corresponding to a default gate-level delay. A voltage scaling factor corresponding to the minimum voltage and default voltage values is determined. The circuit design is synthesized such that the synthesized design includes the voltage scaling value. The synthesized design specifies setting an operating voltage to a value of a startup voltage value scaled by the voltage scaling value.

Device specific configuration of operating voltage

A system and method for providing transparent communications between an Infiniband (IB) network and a Fibre Channel (FC) network are disclosed. One method comprises: (a) detecting FC node ports in the FC network; (b) creating virtual IB targets for each FC node port in the FC network; and (c) converting IB packets directed to the virtual IB targets into FC frames directed to the corresponding FC node port. It may further comprise intercepting management packets directed to the virtual IB targets and responsively emulating a subnet management agent (SMA) of the addressed virtual IB target. Another method comprises: (a) detecting IB channel adapters; (b) creating a virtual FC target for each IB channel adapter; and (c) converting any FC frames directed to the virtual FC targets into IB packets directed to the corresponding IB channel adapter. Fabric frames directed to the virtual FC targets may be intercepted and handled appropriately.

Method and apparatus for transparent communication between a fibre channel network and an Infiniband network

An Inifiniband (IB) network that incorporates a Fibre Channel (FC) network is disclosed. The IB and FC networks are coupled by a gateway that maps the FC network to a virtual IB network. In generating the virtual IB network, the gateway may provide a virtual IB target for each node port in the FC network, and may further provide a minimum number of virtual IB switches necessary to support the virtual IB targets. The gateway assigns a globally unique identifier (GUID) to each of the virtual IB targets, and may further associate local identifiers (LID) with the virtual IB targets. The gateway preferably emulates subnet management agents (SMA) and general service agents (GSA) of the virtual IB targets when management IB packets are received, and the gateway preferably converts non-management IB packets directed to the virtual IB targets into FC frames directed to the corresponding target FC devices.

Method and apparatus for mapping between a fibre channel network and an infiniband network

Method and apparatus for transparent communication between a fibre channel network and an infiniband network

Placing virtualization agents in the switches which comprise the SAN fabric. Higher level virtualization management functions are provided in an external management server. Conventional HBAs can be utilized in the hosts and storage units. In a first embodiment, a series of HBAs are provided in the switch unit. The HBAs connect to bridge chips and memory controllers to place the frame information in dedicated memory. Routine translation of known destinations is done by the HBA, based on a virtualization table provided by a virtualization CPU. If a frame is not in the table, it is provided to the dedicated RAM. Analysis and manipulation of the frame headers is then done by the CPU, with a new entry being made in the HBA table and the modified frames then redirected by the HBA into the fabric. This can be done in either a standalone switch environment or in combination with other switching components located in a director level switch. In an alternative embodiment, specialized hardware scans incoming frames and detects the virtualized frames which need to be redirected. The redirection is then handled by translation of the frame header information by hardware table-based logic and the translated frames are then returned to the fabric. Handling of frames not in the table and setup of hardware tables is done by an onboard CPU.

Hardware-based translating virtualization switch

A circuit measures the signal propagation delay through a selected test circuit. The test circuit is provided with a feedback path so that the test circuit and feedback path together form a free-running oscillator. The oscillator then automatically provides its own test signal that includes alternating rising and falling signal transitions on the test-circuit input node. A phase discriminator samples the output of the oscillator and accumulates data representing the signal propagation delay of either rising or falling signal transitions propagating through the test circuit. The worst-case delay associated with the test circuit can then be expressed as the longer of the two. Knowing the precise worst-case delay allows IC A designers to minimize the guard band and consequently guarantee higher speed performance.

Built-in self test using pulse generators

A circuit measures the signal propagation delay through a selected test circuit. The test circuit is provided with a feedback path so that the test circuit and feedback path together form a free-running oscillator. The oscillator then automatically provides its own test signal that includes alternating rising and falling signal transitions on the test-circuit input node. A phase discriminator samples the output of the oscillator and accumulates data representing the signal propagation delay of either rising or falling signal transitions propagating through the test circuit. The worst-case delay associated with the test circuit can then be expressed as the longer of the two. Knowing the precise worst-case delay allows IC designers to minimize the guard band and consequently guarantee higher speed performance.

Built-in AC self test using pulse generators

A circuit measures the signal propagation delay through a selected test circuit. The test circuit is provided with an inverting feedback path so that the test circuit and feedback path together form a free-running oscillator. The oscillator then automatically provides its own test signal that includes alternating rising and falling signal transitions on the test-circuit input node. These signal transitions are counted over a predetermined time period to establish the average period of the oscillator. Finally, the average period of the oscillator is related to the average signal propagation delay through the test circuit. One embodiment of the invention includes a phase discriminator that samples the output of the oscillator and accumulates data representing the duty cycle of that signal. The duty cycle can then be combined with the average period of the test signal to determine, separately, the delays associated with falling and rising edges propagating through the test circuit.

Method and system for measuring signal propagation delays using ring oscillators

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San Ramon, CA, United States of America

Daniel Y Chung