Discovision Associates

Asahi Kasei Microsystems Co., Ltd.

Nikon Corporation

Daniel Wu

Nob Kimura

Shiro Suzuki

The present invention includes a method and apparatus for reducing the width of a mark written in optical media. When forming a long mark, the prior art recording methods typically cause blooming at the edges of the mark, resulting in a wide mark pattern which may be sensed by the read focused spot reading an adjacent track causing increased adjacent track crosstalk (ATC). However, by removing every other pulse from the write pulse waveform, the cooling sequence of the writing process is sufficiently increased to allow for additional cooling between pulses. When forming marks with less pulses, the effects of blooming are substantially reduced. Thus, because of the reduction in the effect of blooming, the problems associated with ATC, whereby adjacent track information is recorded, is substantially reduced.

Method and apparatus for reducing the width of marks written in optical media

Method and apparatus for reducing the width of marks written in optical

The present invention includes a method and apparatus for reducing the signal amplitude in long marks which are written into optical disks. When forming a long mark, an increased signal amplitude is typically caused by the blooming toward the end of the mark, and is often sensed by the focused spot in the adjacent track causing increased adjacent track crosstalk (ATC). However, when forming short marks, the effect of blooming is minimized. Therefore, by splitting a long mark into a sequence of short period marks, with short period spaces (1T) between each short period mark, the effect of blooming is substantially reduced.

Dividing marks in optical media to decrease adjacent track crosstalk

A clock combining circuit includes a FIFO circuit, a signal combining circuit and a signal selecting circuit. The FIFO circuit accepts, for example, a positive-edge playback signal RDATA0 that has as data the positive edge of a playback signal obtained from recording domains formed in a recording medium, RDATA0 being synchronized with a positive-edge clock signal RCLK0. The FIFO circuit also accepts a negative-edge playback signal RDATA1 that has as data the negative edge of the playback signal, RDATA1 being synchronized with a negative-edge clock signal RCLK1. The FIFO circuit causes RDATA0 and RDATA1 to be synchronized with RCLK0 so as to output a delayed positive-edge playback signal RDATA0D and a delayed negative-edge playback signal RDATA1D. The delayed negative-edge playback signal is delayed by -KT to +LT, where K and L are integers and T is the clock period. The signal combining circuit combines the delayed positive-edge and negative-edge playback signals, and outputs (K+L+1) combined signals. The signal selecting circuit detects marks contained in the playback signal, the marks being independent of the (K+L+1) combined signals, and outputs selected ones of the combined signals based on the detected marks.

Clock combining circuit

An information playback apparatus includes a clock combining circuit having a FIFO circuit, a signal combining circuit and a signal selecting circuit. The FIFO circuit accepts, for example, a positive-edge playback signal RDATA0 that has as data the positive edge of a playback signal obtained from recording domains formed in a recording medium, RDATA0 being synchronized with a positive-edge clock signal RCLK0. The FIFO circuit also accepts a negative-edge playback signal RDATA1 that has as data the negative edge of the playback signal, RDATA1 being synchronized with a negative-edge clock signal RCLK1. The FIFO circuit causes RDATA0 and RDATA1 to be synchronized with RCLK0 so as to output a delayed positive-edge playback signal RDATA0D and a delayed negative-edge playback signal RDATA1D. The delayed negative-edge playback signal is delayed by -KT to +LT, where K and L are integers and T is the clock period. The signal combining circuit combines the delayed positive-edge and negative-edge playback signals, and outputs (K+L+1) combined signals. The signal selecting circuit detects marks contained in the playback signal, the marks being independent of the (K+L+1) combined signals, and outputs selected ones of the combined signals based on the detected marks.

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Cerritos, CA, United States of America

Daniel Wu