Lsi Logic Corporation

Swift Microelectronics Corporation

Daniel Wong

Anthony Yap Wong

Steven S Chan

Conrad J Dell'Oca

Roger T Szeto

Brian Cheung

Alex C Hui

Anna Tam

Eric Chan

A repeating cell structure in a semiconductor substrate for a BiCMOS logic gate array. The cell structure has three regions shaped as columns. The first columnar region is a P-well and has four vertically aligned active areas of N-type material formed within the columnar region. Each of the active areas has two gate electrodes to form two NMOS transistors. Similarly the second columnar region is a N-well and has four vertically aligned active areas of P-type material. Each such active region forms two PMOS transistors. The third column has two bipolar transistors, each with collector, base and emitter regions vertically aligned. The resulting BiCMOS logic array permits a flexible location of macrocells, which results in a compact implementation of the resulting integrated circuit.

BiCMOS compacted logic array

A CMOS driver circuit which differentially drives a pair of transmission lines at a first terminal in response to a signal on the CMOS driver circuit's input terminal for reception of said signal at a second terminal is provided. The driver circuit has two pairs of drive transistors. Each drive transistor has first and second source/drains and a gate. Each drive transistor pair is connected to one of said transmission line pair, and has a NMOS transistor and a PMOS transistor.

CMOS Differential driver circuit for high offset ground

An embodiment of the present invention is a customizable integrated circuit including a basic cell diffusion of four transistors in a substrate. A first metallization layer includes a plurality of connective strips that electrically connect to the basic cell by a plurality of contacts. A second metallization layer, after a first patterning and chemical etch, comprises an orthogonal matrix of conductors that are electrically connected to corresponding connective strips by a plurality of vias that are respectively positioned at an intersection of orthogonal conductors. A second patterning and chemical etch of the second metallization layer configures the basic cell according to a user's specification.

Application specific integrated circuit and placement and routing

A gate array is provided in which active areas within the substrate are arranged in alternating columns of opposite conductivity type and symmetrical about the center lines through each column so that CMOS devices can be advantageously formed by allocating only small increments of active area to metal routing. The substrate and well taps are also symmetrical about the column center line. The active area symmetry allows p-channel and n-channel transistors to be combined where the p-channel transistor is on either the right or left, thus increasing the flexibility in placing the elements within the integrated circuit chip.

Double metal HCMOS compacted array

A CMOS driver circuit for integrated circuits capable of operating in two modes. The first, high speed, mode allows the driver circuit on an integrated circuit device to drive the internal signals of the device to the outside world for standard operation of the integrated circuit devices. The second mode causes the driver circuit to behave as a weak driver for easily testing the integrated circuit.

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San Jose, CA, United States of America

Daniel Wong