Compaq Information Technologies Group, L.p.

Hewlett-packard Development Company, L.p.

Compaq Computer Corporation, Inc.

Daniel William Bailey

Mark D Matson

Shane Bell

Jeffrey D Pickholtz

Richard B Watson, Jr

William Johnson Bowhill

Stephen Felix

Ronald P Preston

Jason F Cantin

Daniel E Dever

Jeff L Chu

Stephen E Liles

Frame

A digital delay locked loop (DLL) includes a phase detector that measures the phase difference between a signal to be synchronized and a reference signal. The phase detector produces an increase or decrease signal in response to the phase difference between the two signals. This signal is received by a binary counter, which changes its count in response. The output of the binary counter is supplied to a comparator logic that implements a thermometer coding scheme. Each of the comparator output signals enables or disables a corresponding transistor stack in a delay line, thereby changing the delay of the signal propagating through the delay line.

Expanded comparator for control of digital delay lines in a delay locked loop or phase locked loop

A clock driver is disclosed that minimizes propagation delay, and thus improves the integrity of a clock distribution network. The clock driver preferably is implemented with silicon-on-insulator (SOI) technology, and comprises an inverter with an nFET and pFET that are body-connected. The body connection serves to reduce the body voltage of the pFET, while increasing the body voltage of the nFET. This shifting of the voltage reduces the voltage threshold differential for both the nFET and pFET, which translates into a design that experiences less propagation delay due to voltage variations and fluctuations. If desired, the body voltages may be slightly offset from each other by placing one or more voltage drop transistors in the conductive path between the bodies of the nFET and pFET. In addition, the present invention may be used to design a programmable inverter that can operate in a low power mode, or in a high precision mode.

Low threshold voltage silicon-on-insulator clock gates

A conditional clock gate is implemented that equalizes load conditions on clocked transistor gates to provide a better quality clock signal in a clock distribution network. The conditional clock gate may be implemented as either a NAND gate or a NOR gate. According to one embodiment, a pre-charge transistor is that equals clock loading when the enable signal is de-asserted. The pre-charge transistor charges a terminal of a clocked transistor during certain clock states to mimic load conditions that exist when the enable signal is asserted. In another embodiment, a pre-discharge transistor is implemented that charges a terminal of a clocked transistor during certain clock states to mimic load conditions that exist when the enable signal is asserted. Conditional clock gates may also be implemented with multiple enable inputs using these same prnciples.

Conditional clock gate that reduces data dependent loading on a clock network

A computer system employs a sense amplifier having set and reset functions incorporated therein. Those functions can be performed by the sense amplifier rather than by circuits connected to the sense amplifier. The set and reset functionality is added to the sense amplifier in a manner that minimally impacts the sense amplifier's performance. Accordingly, the sense amplifier includes a number of discharge paths for discharging charges that develop on its output terminals. The set and reset circuit includes a number of high conductance paths that are turned-on in response to an assertion of a set control signal or a reset control signal. When either of those control signals is asserted, the corresponding output terminal is discharged. Accordingly, the output terminals can be either set or reset, responsive to which of the control signals is asserted. When the control signals are de-asserted, the sense amplifier performs in a normal sense amplifier manner.

Settable digital CMOS differential sense amplifier

A multi-ported SRAM memory cell includes a pair of inverters that holds the data bit. The state terminals of the memory cell connect via a separate read and write data path to the bit lines. The read bit lines connect to a pull-down transistor stack. The first transistor in the stack is gated by the word line, and the second transistor is gated by the state terminal of the memory cell. If the word line is asserted and the second transistor is turned on by the state of the memory cell, the bit line is connected to ground, thus pulling the bit line low. Conversely, if the second transmitter is not turned on, the bit line stays at a high voltage level. In a preferred embodiment, the memory cell is isolated from the pull-down transistor stack by an isolation buffer, such as an inverter, which inverts the voltage on the state terminal of the memory cell. The write data path couples to the memory cell through an access transistor, and also through a second gate that operates to restrict current leakage from the bit lines. In the preferred embodiment, the second gate comprises a current choke that limits current flow to the memory cell during a read operation. Alternatively, the second gate may comprise a transistor that is gated by a write enable signal.

Multi-ported SRAM cell with shared bit and word lines and separate read and write ports

A clock distribution system for a semiconductor device provides for both on-chip and in-package clock distribution via on-chip and in-package clock distribution networks. Each of these networks is selectively enabled depending on the mode of operation. Specifically, for wafer testing, the on-chip clock distribution network is selected. Thus, a probe tester need only provide a single clock source with conventional timing specifications to test the operation of the chip. In contrast, during normal operation, an in-package clock distribution network is enabled. In-package clock routing provides the lowest variation mode and thus, will result in the maximum clock frequency for the chip.

Dual on-chip and in-package clock distribution system

A method and apparatus are provided for ensuring that a clocked circuit will function after fabrication, regardless of the presence of clock skew. More particularly, a method and apparatus are shown for de-skewing the clock signals of such a clocked circuit only when clock skew is present. When such clock skew does not develop, peak performance of the associated circuit can be achieved by turning off the de-skewing function without removing that functionality from the circuit.

Method and apparatus to enforce clocked circuit functionality at reduced frequency without limiting peak performance

Set and reset functions are corporated in a sense amplifier such that those functions can be performed by the sense amplifier rather than by circuits connected to the sense amplifier. The set and reset functionality is added to the sense amplifier in a manner that minimally impacts the sense amplifier's performance. Accordingly, the sense amplifier includes a number of discharge paths for discharging charges that develop on its output terminals. The set and reset circuit includes a number of high conductance paths that are turned-on in response to an assertion of a set control signal or a reset control signal. When either of those control signals is asserted, the corresponding output terminal is discharged. Accordingly, the output terminals can be either set or reset, responsive to which of the control signals is asserted. When the control signals are de-asserted, the sense amplifier performs in a normal sense amplifier manner.

A method and apparatus are provided for improving the data hold timing requirement of the sense amplifier by coupling a pass-gate to its data input ports. Each pass-gate receives a logic level that has developed on an input data signal. When the data is valid, a control signal is asserted that causes the pass-gate to latch the logic level at the input of the sense amplifier. While that logic level is latched, the sense amplifier can generate a corresponding latched output signal and the data signal can transition to a new logic level. Therefore, the pass-gate maintains the logic level at the input of the sense amplifier for the duration of the data hold timing requirement. The pass-gate can be a level-sensitive latch that latches said first logic level in response to the assertion level of the control signal. It includes a first transistor having a drain terminal connected to the data signal, a source terminal connected to the sense amplifier and a gate terminal connected to the control signal. That transistor can be a PMOS or NMOS transistor.

Pass-gate inputs that temporarily hold state on a high input impedance, strobed CMOS differential sense amplifier

The sense amplifier of the present invention senses the logic level of a digital data element that is conveyed using a low voltage swing signal. That sensing operation occurs relatively soon after the logic level of the data element begins to be established at the input of the sense amplifier. Such a sense amplifier is referred to as having increased sensitivity due to an improved common mode rejection ratio. The common mode rejection ratio is improved by turning-on a pair of evaluate transistors in a successive manner. The sense amplifier includes a pair of discharge paths for allowing a charge, stored on associated internal signals, to be discharged at a given rate that is proportional to voltage levels of the associated data signals. Those data signals are isolated from the discharge paths such that the associated logic levels are not affected by the above mentioned discharge operation. An evaluate unit is connected to the discharge paths and conveys a first portion of the above mentioned charge to electrical ground at an initial rate. At a later time, the evaluate unit conveys a second portion of charge to electrical ground at a subsequent rate, such that the sensitivity of the sense amplifier is improved.

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Northboro, MA, United States of America

Daniel William Bailey