Commsky Technologies Corporation

Promos Technologies, Inc

Adesto Technologies Corporation

Actel Corporation, Inc.

Daniel Wang

Jun Shen

Po-shin Cheng

George Zhao

Xin Li

Chunchieh Huang

Jin-Ho Kim

Shane Charles Hollmer

John Dinh

Nad Edward Gilbert

Chia-Shun Hsiao

Barbara Haselden

Derric Lewis

John Ross Jameson

Kuei-Chang Tsai

Dong Jun Kim

Venkatesh P Gopinath

Deepak Kamalanathan

Juan Pablo Saenz Echeverry

Janet Wang

An antenna system having a dynamic radiation pattern is provided. The antenna system comprises at least one antenna unit that includes an antenna dipole, a plurality of reflectors disposed around the antenna dipole, and a plurality of switches each corresponding to one of the reflectors. Each of the switches is coupled between the corresponding reflector and an electrical ground of the antenna system. The antenna system further includes a control unit configured to dynamically change a radiation pattern of the antenna system by controlling the plurality of switches.

Antenna system having dynamic radiation pattern

Techniques of designing an antenna array or antenna system are described. The antenna system includes a plurality of antenna units structured in a way to form a desired antenna pattern. According to one aspect of the present invention, each of the antenna units includes two antennas disposed orthogonally or in parallel. These antenna units are arranged in a pre-defined geometric pattern to create two substantially similar main beam radiation characteristics for independent polarizations.

Antenna systems providing simultaneously identical main beam radiation characteristics

Techniques of designing an antenna array with antenna units controlled electronically are described. Through controlling the combination of the reflectors in each of the antenna units, a desired antenna pattern is formed, adapting to the environment, and providing reliable and efficient links between two transceivers. According to one aspect of the present invention, a switch (e.g., a diode) is used to couple two reflectors. The diode is controlled to be on or off so that the reflectors are conductively integrated or separated.

Switchable antennas for wireless applications

Techniques of designing a smart antenna system are described. An antenna system includes at least two integrated antenna units arranged with a predefined angular angle therebetween to form a desired antenna pattern without any significant nulls. According to one aspect of the techniques, at least two sets of antenna units are interlaced but polarized differently to form an integrated antenna unit. Each of the antenna units is formed with an array of antennas. The antennas in an array or the antenna units in an integrated antenna unit can be selectively energized to form a desired antenna pattern in accordance with a signal determined from radio frequency signals communicated between a device equipped with the antenna system and another device (e.g., a Wi-Fi router in communication with a mobile device), where the desired antenna pattern provides an optimized antenna pattern to facilitate seamless or QoS communication between the two devices.

Multi-channel multi-sector smart antenna system

In one embodiment, a semiconductor memory device includes a plurality of resistive switching memory cells, where each resistive switching memory cell can include: (i) a programmable impedance element having an anode and a cathode; (ii) a word line pair configured to control access to the programmable impedance element, where the word line pair comprises first and second word lines; (iii) a PMOS transistor having a source coupled to the cathode, a drain coupled to a bit line, and a gate coupled to the first word line; and (iv) an NMOS transistor having a source coupled to the bit line, a drain coupled to the cathode, and a gate coupled to the second word line.

Resistive switching memory with cell access by analog signal controlled transmission gate

Techniques of designing an antenna array with antenna units controlled electronically are described. Each of the antenna units includes a reflector, a driven element and one or more directors. A substrate with conductive material on its surface provided to support the antenna array is designed to be the reflector. The driven element is separated into two halves with each on one side of a non-metal substrate vertically bonded to the conductive substrate. Two driving lines provided to drive the two halves of the driven element are disposed on both sides of the non-metal substrate to minimize possible interactions with other elements of the antenna unit or the antenna array.

Antenna arrays with modified Yagi antenna units

Structures and methods for control of an operating window of a programmable impedance element are disclosed herein. In one embodiment, a semiconductor memory device can include: (i) a memory array having a programmable impedance element; (ii) a register configured to be programmed with data that represents an erase verify value, a program verify value, and a read trip point resistance value, for the memory array; (iii) a controller configured to determine a mode of operation for the memory array; (iv) a register access circuit configured to read the register to obtain data that corresponds to the mode of operation; and (v) a voltage generator configured to generate a reference voltage based on the register data, where the reference voltage is used to perform an operation on the programmable impedance element corresponding to the mode of operation.

Programmable window of operation for CBRAM

A memory device can include a plurality of programmable elements; at least one sense circuit that generates sense data values from detected impedances of accessed programmable elements; and at least one data store circuit that stores initial data values from the at least one sense circuit, and stores output data values from the at least one sense circuit after check conditions have been applied to at least one programmable element. The check conditions can induce a change in impedance for programmable elements programmed to at least one predetermined state. Methods can include reading data from at least one memory cell of a memory device comprising a plurality of such memory cells; if the read data has a first value, providing such data as an output value; and if the read data has a second value, repeating access to the memory cell to confirm the read data value.

Read methods, circuits and systems for memory devices

Substrate isolation trench () are formed in a semiconductor substrate (). Dopant (e.g. boron) is implanted into the trench sidewalls by ion implantation to suppress the current leakage along the sidewalls. During the ion implantation, the transistor gate dielectric () faces the ion stream, but damage to the gate dielectric is annealed in subsequent thermal steps. In some embodiments, the dopant implantation is an angled implant. The implant is performed from the opposite sides of the wafer, and thus from the opposite sides of each active area. Each active area includes a region implanted from one side and a region implanted from the opposite side. The two regions overlap to facilitate threshold voltage adjustment.

Substrate isolation in integrated circuits

Nonvolatile memory wordlines () are formed as sidewall spacers on sidewalls of control gate structures (). Each control gate structure may contain floating and control gates (), or some other elements. Pedestals () are formed adjacent to the control gate structures before the conductive layer () for the wordlines is deposited. The pedestals will facilitate formation of the contact openings () that will be etched in an overlying dielectric () to form contacts to the wordlines. The pedestals can be dummy structures. A pedestal can physically contact two wordlines.

Use of pedestals to fabricate contact openings

In integrated circuit fabrication, an etch is used that has a lateral component. For example, the etch may be isotropic. Before the isotropic etch of a layer (), another etch of the same layer is performed. This other etch can be anisotropic. This etch attacks a portion (X) of the layer adjacent to the feature to be formed by the isotropic etch. That portion is entirely or partially removed by the anisotropic etch. Then the isotropic etch mask () is formed to extend beyond the feature over the location of the portion subjected to the anisotropic etch. If that portion was removed entirely, then the isotropic etch mask may completely seal off the feature to be formed on the side of that portion, so the lateral etching will not occur. If that portion was removed only partially, then the lateral undercut will be impeded because the passage to the feature under the isotropic etch mask will be narrowed.

Use of multiple etching steps to reduce lateral etch undercut

A metal-to-metal antifuse according to the present invention is compatible with a Cu dual damascene process and is formed over a lower Cu metal layer planarized with the top surface of a lower insulating layer. A lower barrier layer is disposed over the lower Cu metal layer. An antifuse material layer is disposed over the lower barrier layer. An upper barrier layer is disposed over the antifuse material layer. An upper insulating layer is disposed over the upper barrier layer. An upper Cu metal layer is planarized with the top surface of the upper insulating layer and extends therethrough to make electrical contact with the upper barrier layer.

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San Jose, CA, United States of America

Daniel Wang