International Business Machines Corporation

Samsung Electronics Co., Ltd.

Daniel Waddington

Chen Tian

Jilong Kuang

Mark Kunitomi

Saransh Gupta

Ahmet Serkan Ozcan

Mario Blaum

Clement Lambert Dickey

Tongping Liu

Luna Xu

Juan Colmenares

Amir Abboud

Samyukta Satish Rao

An embodiment includes a virtual machine (VM) memory synchronization process for improved failure tolerance. The process includes writing, by an intelligent memory controller (IMC), current snapshot data to a first series of contiguous memory addresses, where the current snapshot data is received by the IMC from a memory of an active VM via a direct memory access (DMA) transfer operation. The IMC executes concurrent threads associated with respective spans of the contiguous memory addresses, where the concurrent threads control compression processing of respective portions of the current snapshot data resulting in corresponding portions of processed current snapshot data, where the concurrent threads comprise a thread bound to a hardware accelerator that performs the compression processing of a portion of the current snapshot data. The process then transmits the processed current snapshot data to a standby VM as a current synchronization snapshot of the active VM.

Accelerated encoding for virtual machine synchronization

Embodiments of the present disclosure provide an enhanced system and methods for optimizing data placement in a memory hierarchy. A disclosed non-limiting computer-implemented method configures a counter block comprising access frequency counters mapped into an application memory space, and configures a counter map, where each entry in the counter map associates an application-defined memory region with the access frequency counters of the counter block. A memory controller identifies a memory access in a given application-defined memory region and compares an access address with a mask in the counter map to track the memory access. The memory controller generates a heatmap representing a frequency count of accesses to quantized memory using the access frequency counters. Generating the heatmap is performed by memory controller hardware.

Optimizing memory management using memory access heatmaps

A computer-implemented method according to one embodiment includes receiving a request to perform a transaction in persistent memory at a first node; implementing the transaction within a volatile transaction cache at the first node; determining parity data for the transaction at the first node; sending the parity data from the first node to a parity node; and transferring results of the transaction from the volatile transaction cache to the persistent memory at the first node.

Implementing erasure coding with persistent memory

A bioinformatics method is provided for identifying candidate biological sequences, such as DNA, RNA, and proteins, with high sensitivity and specificity for application in procedures such as PCR and gene and protein sequencing. The method involves categorizing a collection of biological sequences within an out-group and an in-group, identifying the intersection between the in-group and the out-group, the union of the out-group, and a relative complement of sequences that are members of the in-group, but not the out-group. A biological signature for a species of interest with high sensitivity and specificity will be a member of the relative complement that has an out-group frequency of zero.

Discovery of biological signatures of optimized sensitivity and specificity

A computer-implemented method according to one aspect includes receiving a request to perform a transaction in persistent memory; determining a correlation between volatile memory address locations in a volatile transaction cache and persistent memory locations in the persistent memory; performing the transaction within the volatile memory address locations of the volatile transaction cache; identifying modified volatile memory address locations in the volatile transaction cache that have been written during the transaction; logging, within the persistent memory, data within the modified volatile memory address locations; copying the data within the modified volatile memory address locations to corresponding persistent memory locations in the persistent memory, utilizing the determined correlation; and removing the logged data from the persistent memory, in response to determining that the copying has completed.

Implementing crash consistency in persistent memory

A computer-implemented method includes receiving genomic data associated with a plurality of genomes and identifying k-mer sets within the genomic data. The method includes constructing a k-mer subset tree according to the following process: performing iterative pairwise comparisons on the k-mer sets, wherein the iterative pairwise comparisons identify fragments with the most shared k-mers, merging the identified fragments into non-leaf nodes of the k-mer subset tree, and placing each remaining k-mer into a leaf node of the k-mer subset tree. The method includes storing the k-mer subset tree. A computer program product for data compression includes a computer readable storage medium having program instructions embodied therewith. The program instructions are executable by a computer to cause the compute to perform the foregoing method. A system includes a processor and logic. The logic is configured to perform the foregoing method.

K-mer based genomic reference data compression

A computer-implemented method includes receiving data structures in memory space and creating micro-heaps on a per-data structure basis. Each data structure is associated with a micro-heap allocator. The method also includes storing the data structures in a key-value store. Values of the key-value store are associated with the data structures. A computer program product includes one or more computer readable storage media, and program instructions collectively stored on the one or more computer readable storage media. The program instructions include program instructions to perform the foregoing method. A system includes a processor and logic integrated with the processor, executable by the processor, or integrated with and executable by the processor. The logic is configured to perform the foregoing method.

Pointer-based dynamic data structures in key-value stores

A computer-implemented method is provided for neuromorphic computing in a Dynamic Random Access Memory (DRAM). The method includes representing one or more neurons by memory rows in the DRAM. Each bit in any of the memory rows represents a single synapse. The method further includes responsive to activating a given one of the neurons, reinforcing an associated synaptic state of a corresponding one of the memory rows representing the given one of the neurons. The method also includes responsive to inhibiting the given one of the neurons, degrading the associated synaptic state of the corresponding one of the memory rows representing the given one of the neurons.

Neuromorphic computing in dynamic random access memory

A computer-implemented method according to one embodiment includes identifying a communication channel associated with a user-level stack within a user space of a system, establishing a user space communications path with the user-level stack, utilizing the communication channel and shared memory within the user space of the system, and redirecting one or more calls within the user space of the system to the user-level stack, utilizing the user space communications path.

Integrating kernel-bypass user-level file systems into legacy applications

One embodiment provides a caching system comprising a hash table, a network interface for receiving a sequence of network-level packets for caching, and a caching application module for storing the sequence of network-level packets in the hash table. The sequence of network-level packets is stored its original form without de-fragmentation.

Caching architecture for packet-form in-memory object caching

One embodiment comprises a hierarchical heap allocator system. The system comprises a system-level allocator for monitoring run-time resource usage information for an application having multiple application threads. The system further comprises a process-level allocator for dynamically balancing resources between the application threads based on the run-time resource usage information. The system further comprises multiple thread-level allocators. Each thread-level allocator facilitates resource allocation and resource deallocation for a corresponding application thread.

Quota-based adaptive resource balancing in a scalable heap allocator for multithreaded applications

Task management in a Non-Uniform Memory Access (NUMA) architecture having multiple processor cores is aware of the NUMA topology in task management. As a result memory access penalties are reduced. Each processor is assigned to a zone allocated to a memory controller. The zone assignment is based on a cost function. In a default mode a thread of execution attempts to perform work in a queue of the same zone as the processor to minimize memory access penalties. Additional work stealing rules may be invoked if there is no work for a thread to perform from its default zone queue.

NUMA aware system task management

Memory management includes maintaining a first mapping structure for each thread of a multi-threaded process. A second mapping structure is maintained for each core of a multi-core processing device. A global mapping structure for shared memory mappings is maintained. During thread context switches, copying thread context entries without modifying a page-mapping base address register of each core of the multi-core processing device.

Multi-threaded memory management

An architecture for multi-core and many-core processor systems includes a set of resource managers having a hierarchy of at least one level. The resource managers act as trusted proxies for the operating system (OS) kernel to manage resources for applications. The application may include a trusted secure specification defining resource and access privileges of the associated application.

Scalable and secure application resource management and access control for multicore operating systems

In a shared memory process different threads may attempt to access a shared data variable in a shared memory. Locks are provided to synchronize access to shared data variables. Each lock is allocated to have a location in the shared memory relative to the instance of shared data that the lock protects. A lock may be allocated to be adjacent to the data that it protects. Lock resolution is facilitated because the memory location of a lock can be determined from an offset with respect to the data variable that is being protected by the lock.

Growing community of inventors

Morgan Hill, CA, United States of America

Daniel Waddington