International Business Machines Corporation

Daniel W Storaska

Louis L Hsu

Michael Anthony Sorna

Jeremy K Stephens

John Atkinson Fifield

Toshiaki Kirihata

Karl David Selander

Rajiv V Joshi

Wing Kin Luk

Joseph Natonio

William Richard Kelly

Claude Louis Bertin

William R Tonti

Wolfgang Sauter

Li-Kong Wang

Chandrasekhar Narayan

Hiroyuki Akatsu

Troy James Beukema

Ciaran J Brennan

Chorng-Lii Hwang

Edward R Pillai

Hibourahima Camara

William F Washburn

Nick Van Heel

A serial data receiver includes an amplitude path including a first signal conditioner that adds a first offset or subtracts a second offset based on a selection input, a preamp configured to receive a signal from a transmitter and provide an input signal to the amplitude path, an amplitude latch coupled to the amplitude path, a data latch having a data output and a decision feedback equalization (DFE) logic block coupled to the first conditioning element and the data output and configured to generate the selection output based on the data output of the data latch.

Post-equalization amplitude latch-based channel characteristic measurement

A phase locked loop ('PLL') includes a voltage controlled oscillator ('VCO') operable to acquire and maintain lock at a selected output frequency of the VCO and control logic operable to perform steps in a method of selecting a frequency band for operating the VCO. Such method can include switching the VCO to a given operating band from among the plurality of operating bands of the VCO; determining a band center frequency at which the VCO oscillates in the given operating band when the control voltage is set to a center of a range of minimum to maximum control voltages [CVmin, CVmax]; determining a difference between the band center frequency and the selected output frequency when the selected output frequency is within the given operating band; switching the VCO to another operating band; repeating the above steps until a difference between the band center frequency and the selected output frequency increases; and selecting the operating band for operation of the VCO for which the difference between the band center frequency and the selected output frequency is smallest.

Auto-calibration for ring oscillator VCO

A method is provided for selecting an operating band of a voltage-controlled oscillator ('VCO') of a phase locked loop ('PLL') for which the lock frequency is closest to a center of the frequency range of the operating band. In such method, steps can be performed to determine the maximum and minimum frequencies of the operating band and the center frequency between them. From the center frequency of the operating band and the lock frequency within such operating band, a difference value can then be determined. The operating bands of the PLL can be tested until an operating band having the smallest difference value is determined. The VCO can then be set to such operating band in order for the lock frequency to be closest to the center frequency of the operating band.

Compensation of VCO gain curve offsets using auto-calibration

An apparatus is provided which includes a common signal node operable to conduct a first signal, a first circuit coupled to the common signal node to utilize the first signal and a signal-handling element coupled to the common signal node. The signal-handling element includes an isolating circuit coupled to the first conductor, a second conductor operable to conduct an output of the isolating circuit, and a signal-handling circuit coupled to the second conductor. The signal-handling circuit is operable to perform a signal-handling function in response to the output of the isolating circuit. By virtue of the isolating circuit, the signal-handling circuit and the first circuit are isolated from the second conductor and the signal-handling circuit. Preferably, the achieved isolation permits a communication signal included in the first signal to be conducted within a communication apparatus with less capacitance, and producing less return loss of that signal.

Apparatus and method for reduced loading of signal transmission elements

A design structure for a signal-handing apparatus or communication apparatus is provided which includes a common signal node operable to conduct a first signal, a first circuit coupled to the common signal node to utilize the first signal and a signal-handling element coupled to the common signal node. A signal-handling apparatus may include an isolating circuit coupled to a first conductor, a second conductor to conduct an output of the isolating circuit, and a signal-handling circuit coupled to the second conductor. A signal-handling circuit can perform a signal-handling function in response to the output of the isolating circuit. The signal-handling circuit and the first circuit may be isolated from the second conductor and the signal-handling circuit such that a communication signal may be conducted with less capacitance and be subject to less return loss.

Structure for apparatus for reduced loading of signal transmission elements

An eyewidth of a data signal is determined by steps including: (a) recovering a phase of a clock from a data signal as a sampling clock; (b) shifting the phase of the sampling clock away from the first phase by a count multiplied by predetermined phase amount; (c) sampling the data signal with the shifted sampling clock phase to obtain sample data; d) determining whether the sample data contains error; (e) when the sample data does not contain error, recovering the phase of the clock from the data signal again for use as the first phase of the sampling clock, increasing the count value and repeating steps (b) through (e); and f) when the sample data contains error, determining the eyewidth based on the last shifted phase of the sampling clock prior to determining that the sample data contains error.

System for measuring an eyewidth of a data signal in an asynchronous system

Apparatus and method for counteracting high frequency attenuation of a differential input data signal as the signal is conducted through a data link. A differential input data signal is transmitted from a transmitter to a receiver through a data link. The data eye of the differential input data signal is modified at the transmitter in response to feedback from the receiver where the extent of the data eye of the differential input data signal, after being conducted through the data link, is determined. The feedback to the transmitter, dependent on the determination of the extent of the data eye, controls the data eye at the transmitter and the equalization of the differential input data signal by adapting the differential input data signal to anticipate high frequency attenuation of the differential input data signal in the data link.

Data transceiver and method for equalizing the data eye of a differential input data signal

A chip is provided in which an on-chip matching network has a first terminal conductively connected to a bond pad of the chip and a second terminal conductively connected to a common node on the chip. A wiring trace connects the on-chip matching network to a circuit of the chip. The on-chip matching network includes an electrostatic discharge protection (ESD) circuit having at least one diode having a first terminal conductively connected to the bond pad and a second terminal connected in an overvoltage discharge path to a source of fixed potential. The matching network further includes a first inductor coupled to provide a first inductive path between the bond pad and the wiring trace, a termination resistor having a first terminal connected to the common node, and a second inductor coupled to provide a second inductive path between the wiring trace and a second terminal of the termination resistor.

On-pad broadband matching network

As disclosed herein, a microelectronic circuit and method are provided for improving signal integrity at a transmission line. The circuit includes a programmably adjustable impedance matching circuit which is coupled to a transmission line which includes a programmably adjustable inductive element. The programmably adjustable impedance matching circuit is desirably provided on the same chip as a receiver or transmitter to which the transmission line is coupled, or alternatively, on an element packaged together with the chip that includes the receiver or transmitter. The impedance of the programmably adjustable impedance matching circuit is adjustable in response to control input to improve signal integrity at the transmission line.

Programmable impedance matching circuit and method

A self-timed data communication system for a wide data width semiconductor memory system having a plurality of data paths is provided. The data communication system includes a central data path including at least one junction circuit configured for exchanging data signals between the central data path and the plurality of data paths of the at least one data path. A respective one junction circuit of the at least one junction circuit includes circuitry for controlling resetting the respective one junction circuit for preparation of a subsequent data transfer through the respective one junction circuit in accordance with receipt of an input junction monitor signal indicating that data has been transferred to the respective one junction circuit. The data communication system further includes a plurality of data banks configured for storing data, wherein a corresponding data bank of the plurality of data banks is connected to a respective one data path of the plurality of data paths. The data communication system further includes circuitry for controlling the respective one data path in accordance with receipt of a monitor signal indicating that a data transfer operation has been initiated for transfer of data from the respective one data path. The circuitry for controlling includes circuitry for generating a control signal for controlling resetting of the respective one data path after data is transferred for preparation of a subsequent data transfer operation.

Embedded DRAM system having wide data bandwidth and data transfer data protocol

A self-timed data communication system for a wide data width semiconductor memory system having a plurality of data paths. The data communication system includes a plurality of data banks configured for storing data, wherein a corresponding data bank of the plurality of data banks is connected to a respective one data path of the plurality of data paths. The data communication system further includes circuitry for controlling the respective one data path in accordance with receipt of a monitor signal indicating that a data transfer operation has been initiated for transfer of data to or from the respective one data path. The circuitry for controlling includes circuitry for generating a control signal for controlling resetting of the respective one data path after data is transferred for preparation of a subsequent data transfer operation.

A memory array architecture employs a full Vdd bitline precharged voltage and a low wordline boost voltage, which is less than Vdd plus the threshold voltage of the access transistor. In a write mode, a first low level of a data bit is almost fully written to a storage element, however a second high level of the data bit is not fully written to the storage element. In a read mode, the first low level of the data bit is fully read out from the storage element, however the second high level of the data bit is not read out by utilizing the access transistor threshold voltage. This allows a sensing signal only with the first voltage level transfer to the Vdd precharged BL. A reference WL is preferably used for generating a reference bitline voltage for a differential Vdd sensing scheme. Alternatively, a single BL digital sensing scheme may be used. Lowering the wordline voltage results in a reduction in power consumption by saving power on Vpp generator and support circuits, and a reduction in the size of the Vpp generator and support circuits, and also eliminates high Vpp voltage related problems such as dielectric breakdown and other reliability concerns while avoiding a complex decoding scheme and saving cost.

Method and configuration to allow a lower wordline boosted voltage operation while increasing a sensing signal with access transistor threshold voltage

A writeback and refresh circuit for a direct sense architecture memory wherein a plurality of primary sense amps are connected to a global data line and also to bitlines, each of which is coupled to an array of memory storage cells which are selected for write and read operations by a plurality of wordlines. A single secondary sense amp receives analog level data from the primary sense amps over the global data line, and includes a restore/writeback circuit which digitizes the data and then returns the digitized data over the global data line to the primary sense amp and back into the memory. A 2-cycle read/writeback operation is used for each memory read cycle, a first cycle read operation, and a second cycle writeback operation. The 2-cycle destructive read architecture eliminates the need for a cache and complex caching algorithms.

Writeback and refresh circuitry for direct sensed DRAM macro

A data clock system for a semiconductor memory system is provided for performing reliable high-speed data transfers. The semiconductor memory system includes a plurality of data banks configured for storing data, the plurality of data banks in operative communication with a plurality of first data paths, each first data path in operative communication with a second data path. The data clock system includes a first clock path receiving a clock signal during a data transfer operation for transferring data between one data bank of the plurality of data banks and the second data path via one of the plurality of first data paths; and a second clock path receiving the clock signal from the first clock path and propagating the clock signal along therethrough, the second clock path including at least one clock driver. The transfer of data between the one of the plurality of first data paths and the second data path occurs upon receipt of the clock signal by the at least one clock driver. A method for propagating a clock signal in a semiconductor memory system is also provided for performing reliable high-speed data transfers. In the inventive system and method the clock signal is delayed during propagation along the first clock path and the second clock path by approximately the same amount of time regardless if the at least one clock driver is positioned proximate a far end of the second clock path or the at least one clock driver is positioned proximate a near end of the second clock path.

Semiconductor memory system having a data clock system for reliable high-speed data transfers

A single bitline direct sensing architecture employs a 4 transistor sense amplifier circuit located in each memory array, wherein the transistors function to selectively transfer data bits from either a true bitline or a complement bitline of the bitline pair to a data line. The data line is preferably arranged over a plurality of memory arrays. The data line may or may not be shared for the read and write operations. One current source is additionally used to precharge the datalines in a read mode, performing the function of a digital sensing scheme by detecting a resistance ratio between the current source and the transistor driven by the bitline for the corresponding array. A simple inverter may be used for detecting a level of the data line determined by the resistance ratio. The bitline pair is sensed in a single ended fashion, eliminating the need for a cross-coupled pair of CMOS devices, and thus reducing the required layout area. By accessing the bitline pair individually, two sets of control signals for the pre-charge, EQ EQ are developed to allow for bitline shielding in the array.

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Walden, NY, United States of America

Daniel W Storaska