Freescale Semiconductor,inc.

Daniel W Knox

Thomas L Thomas, Jr

A clock distribution and control system () includes one counter () in a clock generation domain and another counter () in a phase-delayed clock domain. The phase-delayed domain counter () output is combined with a programmable offset value chosen based on the phase delay of the clock distribution system. The result is used to insure that communication between logic in the clock generation clock domain and logic in the phase-delayed clock domain occurs deterministically on the correct clock edge for a range of clock frequencies.

Growing community of inventors

Austin, TX, United States of America

Daniel W Knox