Adaptive Solutions, Inc.

Oregon Graduate Center

Other

Daniel W Hammerstrom

James L Bailey

Dean W Mueller

Stephen G Owens

The sequencer (14) is part of a computational system (10) which includes a computational circuit component, or processor node array (16); the sequencer, or controller component (14); and a boundary interface (34) between the computational circuit component (16) and the controller component (14). The controller component (14) provides three main functions in the system: (one) it sequences computations in a computational component (16), which includes an array of processor nodes (74, 76, 78, 80, 82, 84); (two) it provides I/O processing (20) from several disparate sources between the processor node array (16) and a host processor (12); and (three) it synchronizes data flow from a substantially asynchronous portion of the system (12) with a substantially synchronous data flow in the processor node array portion of the system (16).

Neural network sequencer and interface apparatus

A virtual-zero architecture is intended for use in a single instruction stream, multiple data stream (SIMD) processor which includes an input bus, an input unit, manipulation units, an output unit and an output bus. The virtual-zero architecture includes a memory unit (40) for storing data, an arithmetic unit (42) for mathematically operating on the data, a memory address generation unit (32) and an adder for computing a next memory address. The memory address generation unit (32) includes an address register (34) in the memory unit for identifying the address of a particular data block, a counter (38) for counting the number of memory addresses in a particular data block, and a rotation register (36) for providing a data-void address in the memory unit if and only if all of the entries in the data block are zero. The memory (40) and the address (32) units provide zero-value data blocks to the arithmetic unit (44) to simulate the data block having the data-void address during processing. The architecture may also be used to selectively handle input to a system.

Neural network using virtual-zero

A bit disposal apparatus includes a register (16) which is divided at a truncation point (14) into a left register segment (18) and a right register segment (28), wherein bits to be disposed of are contained in the right register segment. A decision mechanism initially examines the bits in the right register segment (28) and transmits a '1' signal (60) if and only if any of the bits in the right register segment is a '1'. If any of the bits in the right register segment is a '1', a 1 is 'jammed' into the least significant bit location (26a) of a result register (26a). A method of bit disposal includes the steps of setting a truncation point (14) in a register (16), thereby defining left (16) and right (28) register segments (54), loading a binary number into the register (56), examining the bits in the right register segment (58) and transmitting a right register signal which has a '1' value (60) if any of the bits in the right register segment is a '1', and replacing the least significant bit in a result register with a '1' if the right register signal has a '1' value (64).

Unbiased bit disposal apparatus and method

A concurrent computation/communication architecture is intended for use in a single instruction stream, multiple data stream (SIMD) processor node which includes an input bus (20), an input unit (54), manipulation units (58, 60, 62, 64, 66) and an output bus (22). Processor nodes (12, 14, 16, 18) include an output unit (68) which receives data from the input unit (54) and the various manipulation units. Processor nodes (12, 14, 16, 18) store and transmit data from the output unit (68) at a selected time over the output bus (22). A processor node control unit (56) is provided for controlling the exchange of data between the processor nodes (12, 14, 16, 18), their associated output buffers (38, 40, 42, 44) and the output bus (22).

Mechanism providing concurrent computational/communications in SIMD

A hybrid neural-model computational architecture which employs both broadcast hierarchical bus communication for high fan-out communication situations and point-to-point grid communication for low fan-out communication situations.

Neural-model, computational architecture employing broadcast hierarchy

A neural-model-architectural, layered, multidirectional-feed computational system wherein plural groups of computational (connection) nodes are organized by broadcast bus structures into plural, partially overlapping broadcast regions. This organization allows for selective, simultaneous, multidirectional broadcast communication between the groups of nodes in forward, rearward and lateral overlapping regions.

Neural-model computational system with multi-directionally overlapping

A neural-model computational method and architecture structure based on connectionism featuring broadcast-hierarchical, locality-of-communication-dominant operation. According to the hierarchical nature of the invention, the system thereof is organized into plural communication levels, wherein what might be thought of as a lower level handles all communications that take place solely on that level, and what might be thought of as a higher level handles 'long-distance' communications interlevel. Communication takes place in what is referred to herein as a braodcast manner in the sense that a communicating source broadcasts its communication simultaneously to the entirety of that part of the system wherein expected recipients are located. The locality-of-communication-dominance feature groups and organizes the various communication sources generally in accordance with their respective frequencies of communication, assigning addresses, respectively, whose lengths generally relate in an inverse proportion to these frequencies.

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Aloha, OR, United States of America

Daniel W Hammerstrom