Bell & Howell Publication Systems Company

Daniel V Cusick

Raymond G Molnar

Michael A Chmura

John E Conroy

O Nolan Daines

Spoon holder

An image having more pixels than can be displayed on a video monitor (16) is stored in an image buffer (10) in packed raster format. During a vertical retrace period, the video monitor generates several horizontal synchronization signals which clock a video memory controller (20). Each time the video memory controller is clocked, it moves a portion of a next successive row of data from the image buffer to a video memory (12). In this manner, several rows of new data are loaded into the video memory before the video monitor starts withdrawing data from the video memory to display the first raster scan line. As the raster scan line is indexed to move down the video image by the horizontal synchronization pulses, the same horizontal synchronization pulses continue to index the row addresses of the video memory controller keeping the transfer of new data into the video memory several lines ahead of the current raster scan line. In a panning mode, the vertical synchronization signal of the video monitor resets the video memory controller to a new initial starting address (26') shifted a small distance, e.g. one pixel from a preceding data transfer start address (26). This causes the next frame which is displayed to be shifted the small amount from the preceding frame. In this manner, the image is panned smoothly without perceivable flicker.

Accelerated pixel data movement

An image is stored in raster format having N raster or data lines each with M pixel values in an image or print buffer memory (10). An addressing circuit (20) addresses the print buffer memory to read out m.times.n bit columns or blocks of data, where n=N unless cropping of the image is desired. The blocks are parallel loaded alternately into a first FIFO memory array (40) and a second FIFO memory array (62). Each FIFO memory array includes a plurality of FIFO memories (42a-p 64a-p) which store n data lines segments each of m/p bits. In the first n clock cycles of the first FIFO memory (42a), a multiplexer (46) passes the least significant bit (50) of each data line segment read out of the first FIFO memory. The next N times that the first FIFO memory is clocked, the multiplexer passes the next least significant bit and so on until all m/p bits have been passed serially to a laser printer (48). Thereafter, this process is repeated for a second FIFO memory (42b) and each successive one of the p FIFO memories of the first array. After the data in the first array has been serialized, the data in the second FIFO array (62) is serialized as another m.times.n bit column of data is loaded into the first FIFO memory array (40). In this manner, data is serialized and passed to the laser printer (48) in an order which causes data from a horizontal raster line image to be printer along orthogonal data columns (54, 56) on the fly.

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Chesterland, OH, United States of America

Daniel V Cusick