Apple Inc.

Daniel U Becker

Doron Rajwan

Cyril De La Cropte De Chanterac

Achmed Rumi Zahir

Lior Zimet

Ilya Granovsky

Inder M Sodhi

James Nolan Hardage

Richard F Russo

Aditya Kesiraju

Shih-Chieh Wen

Srikanth Balasubramanian

Christopher M Tsay

Venkatram Krishnaswamy

Richard H Larson

Boris S Alvarez-Heredia

Alexander Gendler

Saher Odeh

Techniques are disclosed relating to selective rate limiting and reducing clock frequency of fabric circuitry in response to certain power management events. Disclosed techniques may advantageously allow power management circuitry to reduce or avoid negative impacts of power events by reducing the clock frequency of a communication fabric while using rate limiting of relatively lower-priority traffic to reduce impacts of the frequency reduction on high-priority traffic. For example, rate limiting of lower-quality-of-service virtual channels may continue after recovery of the clock frequency until higher-quality-of-service virtual channels have recovered from the frequency reduction.

Quality-of-service-based fabric power management

An apparatus includes a processing circuit, a power processing module, and a power management circuit. The power management circuit is configured to estimate, over time, energy consumption of the processing circuit, and to sample the estimated energy consumption using a plurality of different sampling frequencies. Each of the different sampling frequencies is used to generate a respective set of power values. The power management circuit is further configured to track a particular characteristic for each set of power values, and then to provide, for each set of power values, a particular power value that corresponds to the particular characteristic to the power processing module. Based on at least one of the particular power values, the power processing module is configured to adjust an operating parameter of the processing circuit.

Tracking power consumption using multiple sampling frequencies

In an embodiment, a local throttling mechanism for the one or more processor cores may support one or more externally-triggered throttling mechanisms. An external source, such as a system-level power manager, may detect an energy-consumption state in the system as a whole and may trigger additional throttling in the processor core throttling mechanism. The externally-triggered throttling may temporarily increase throttling in the processor cores, in an embodiment, decreasing processor core energy consumption to account for the excess energy consumption in other parts of the system.

Externally-triggered throttling

In an embodiment, a power control circuit for an execute circuit is configured to monitor power consumption of operations in a pipeline of the execute circuit and potential changes in power consumption if new operations are issued into the pipeline. The power control circuit may be configured to inhibit issuance of a given operation if the change in power consumption is greater than a maximum increase. A decaying average of previous power consumptions may be maintained and compared to the potential increase in power consumption to control the rate of change in power consumption over time.

Operation processing controlled according to difference in current consumption

In some embodiments, a system includes a plurality of processor cores connected to an energy source. The system further includes one or more budget creation circuits configured to determine respective portions of a total credit budget of the energy source. The system further includes a plurality of credit distribution circuits configured to distribute the respective portions of the total credit budget to respective subsets of the processor cores. The credit distribution circuits share energy credits in response to determining that at least some energy credits will be unused. As a result, energy credits are more likely to be used by the processor cores, as compared to a system where the energy credits are not shared.

Processor energy management system

In some embodiments, a processor core includes an energy tracking circuit and an execution management circuit. The energy tracking circuit is configured to determine an amount of remaining allocated energy of the processor core. The execution management circuit is configured to make a determination whether to stall execution of one or more pipeline operations at the processor core based on a comparison of the amount of remaining allocated energy to a stall threshold. The determination involves applying one or more pseudo-random components to the amount of remaining allocated energy, the stall threshold, or both. The determination is made such that the smaller the amount of remaining allocated energy, the more likely the execution of one or more instructions is to be stalled.

Processor energy consumption rate limiting system

In an embodiment, an integrated circuit may include one or more processors. Each processor may include multiple processor cores, and each core has a different design/implementation and performance level. The processor may support multiple processor states (PStates). Each PState may specify an operating point (e.g. a combination of supply voltage magnitude and clock frequency), and each PState may be mapped to one of the processor cores. During operation, one of the cores is active: the core to which the current PState is mapped. If a new PState is selected and is mapped to a different core, the processor may automatically context switch the processor state to the newly-selected core and may begin execution on that core. The context switch may be performed using a special purpose register (SPR) interconnect. Each processor core in a given processor may be coupled to the SPR interconnect to permit access to the external SPRs.

Hardware migration between dissimilar cores

Embodiments of a computing system that may monitor energy usage are disclosed. The embodiments may provide a low overhead method for determining energy usage of a given application or process. Circuitry is configured to determine a respective energy for each of the plurality of operations and sum each respective energy for at least some of the plurality of operations to generate a normalized total. The circuitry may be further configured to scale the normalized total to generate an energy value, and store the energy value in a register. System software may then read the energy value from the register and determine an energy usage for at least one application dependent upon the energy value.

Low-overhead process energy accounting

In some embodiments, a system includes a plurality of processor cores and a credit distribution circuit. The credit distribution circuit is configured to provide credits to the processor cores. A quantity of the provided credits is based on a total credit budget and requests for additional credits corresponding to the processor cores. The total credit budget is based on an amount of energy available to the processor cores (e.g., made available by a power supply) during a particular window of time. A particular processor core is configured to determine, based on a remaining number of credits for the particular processor core, whether to perform one or more pipeline operations. The particular processor core is further configured to deduct, based on determining to perform the one or more pipeline operations, one or more credits from a remaining quantity of credits allocated to the particular processor core.

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San Jose, CA, United States of America

Daniel U Becker