Altera Corporation

Daniel Tun Lai Chow

San Wong

Peng T Li

Masashi Shimanouchi

Lik Huay Lim

Man On Wong

Vincent K Tsui

Sergey Yuryevich Shumarayev

Weiqi Ding

Mingde Pan

Geping Liu

Siriram Narayan

One embodiment relates to a method of generating worst case inter-symbol interference (ISI) inducing short patterns for simulating and/or testing a communication link. The method includes the generation of a binary clock sequence comprising bits of alternating values at the beginning of the pattern. In addition, an ISI inducing binary sequences and its complement are generated after the clock sequence. Another embodiment relates to a pattern generator for generating an worst case inter-symbol interference inducing short pattern for testing a communication link. Other embodiments, aspects, and features are also disclosed.

Methods and apparatus for generating short length patterns that induce inter-symbol interference

An integrated circuit ('IC') includes circuitry for use in testing a serial data signal. One such IC includes circuitry for transmitting the serial data signal with optional jitter, optional noise, and/or controllably variable drive strength. One such IC also includes circuitry for receiving the serial data signal and performing a bit error rate ('BER') analysis in such a signal. Such an IC provides output signals indicative of results of its operations. One such IC operates in various modes to perform or at least emulate functions of an oscilloscope, a bit error rate tester, etc., for testing signals and circuitry with respect to jitter-tolerance, noise-tolerance, etc.

Circuitry on an integrated circuit for performing or facilitating oscilloscope, jitter, and/or bit-error-rate tester operations

A phase-locked loop is characterized by analyzing phase noise in its output signal while known levels of input phase noise are provided. The resulting data provides intrinsic phase noise and gain of the phase-locked loop. These values provide a general relationship between input phase noise and output phase noise for the phase-locked loop, which allows estimation of output phase noise corresponding to a given level of input phase noise, and allows estimation of input phase noise corresponding to a given level of output phase noise.

Jitter estimation in phase-locked loops

A method for predicting a predetermined bit error rate for an actual data transmission from a transmitter to a target receiver over an actual backplane link is disclosed. The method involves defining a simulated backplane corresponding to an actual backplane link intended to be used for data transmission between a transmitter and a target receiver. Once the simulated backplane is defined, a data transmission from the transmitter to the receiver is simulated and captured across the simulated backplane. A waveform simulation of the data transmission over the simulated backplane is then generated. The waveform simulation takes into account characteristics of the simulated backplane and the target receiver. From the waveform simulation, a total jitter for a predetermined bit error rate for the data transmission is extrapolated.

Transceiver link bit error rate prediction

The present invention is directed to a method and a system to evaluate operational characteristics of an electronic circuit. The method includes generating a visual display, on a monitor, of an eye diagram viewer. The eye diagram viewer is used to establish a test parameter for the circuit. Accessed is data that includes a graphical file containing eye diagram information corresponding to the test parameter. A visually perceivable image of the eye diagram information is provided in response to the test parameter. Specifically, the eye diagram viewer is used to establish an eye diagram information identifier by displaying in a plurality of test condition selector screens one of a multiple condition values for the test condition parameters. The graphical file containing the eye diagram information corresponding to the eye diagram information identifier is obtained from the server and displayed.

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Foster City, CA, United States of America

Daniel Tun Lai Chow