International Business Machines Corporation

Daniel Tuman

Majid Ghafghaichi

Theodore H Baker

Richard Charles Stevens

A method for determining whether an integrated circuit chip containing a plurality of separable circuits is operable when one or more of the separable circuits is not functional. A chip including a plurality of discrete or separable circuits, each of which include means for selectively receiving and distributing a voltage level necessary to render the particular circuit operable, the chip further including a region of one type conductivity at said voltage level common to all of the discrete circuits is tested by a method which will insure that short-circuits between a particular circuit found not to be functional and therefore not to be rendered operable and the common region will not inadvertently apply the voltage level from the common region to voltage receiving and distribution means in the non-functional circuit. All the discrete circuits are first tested to determine which are functional. Then those circuits which fail the functionality test are tested further to detect whether any of these failed circuits have electrical short-circuits between the common region and the means for receiving and distributing said operable voltage level in the failed circuit. If any of the failed circuits have such a short, the chip is considered to be inoperative because such a short will inadvertently connect the failed circuit with the functional circuits.

Integrated circuit structure having a plurality of separable circuits

A planar integrated semiconductor circuit master-slice structure in which the insulation layer over the planar surface remains intact and free of undesirable short-circuit paths in the area beneath excess 'unused' contact terminals which are not part of the selected circuit configuration formed by a selected surface metallization pattern on the insulative layer which selectively interconnects less than all of the contact terminals with less than all of the components extending from the planar surface of a semiconductor substrate beneath the insulative layer. During D.C. sputter cleaning or etching utilized in the formation of the contact terminals and the metallization pattern, there is an undesirable charge accumulation on the unused contact terminals which tends to exceed the dielectric breakdown strength of the insulative layer beneath the terminal. This shorts the unused pad to the semiconductor substrate beneath the terminal. Such short-circuits are avoided by an additional metallization line, not part of the circuit configuration, which connects the unused contact terminal to an unused electrically isolated component e.g. junction isolated component in the semiconductor substrate.

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Daniel Tuman