Intel Corporation

Daniel Towner

Robert Valentine

Mark Jay Charney

Amit Gradstein

Menachem Adelman

Simon C Steely, Jr

Benjamin Keen

Kermin E ChoFleming, Jr

Chuanjun Zhang

An apparatus and method for complex matrix conjugation and multiplication. For example, one embodiment of a processor comprises: a decoder to decode a complex matrix conjugation and multiplication instruction including a first source operand to identify a first complex source matrix comprising a first plurality of complex values, a second source operand to identify a second complex source matrix comprising a second plurality of complex values, and a first destination operand to identify a result matrix; execution circuitry to execute the complex matrix conjugation and multiplication instruction, the execution circuitry comprising: matrix conjugation hardware logic to determine a plurality of complex conjugate values corresponding to the first plurality of complex values; transpose hardware logic to transpose the plurality of complex conjugate values to generate a conjugate transpose matrix comprising the complex conjugate values; parallel multiplication circuitry to: multiply real values from the plurality of complex conjugate values of the conjugate transpose matrix with corresponding imaginary values from the second plurality of complex values to generate a first plurality of imaginary products, and multiply imaginary values from the plurality of complex conjugate values of the conjugate transpose matrix with corresponding real values from the second plurality of complex values to generate a second plurality of imaginary products; and addition/subtraction circuitry to add each imaginary product in the first plurality of imaginary products to a corresponding imaginary product in the second plurality of imaginary products to produce a corresponding imaginary component in the result matrix.

Apparatus and method for conjugate transpose and multiply

An apparatus and method for complex matrix multiplication. For example, one embodiment of a processor comprises: a decoder to decode a first complex matrix multiplication instruction; execution circuitry to execute the first complex matrix multiplication instruction, the execution circuitry comprising parallel multiplication circuitry to multiply real values from the first plurality of real and imaginary values with corresponding real values from the second plurality of real and imaginary values to generate a first plurality of real products, to multiply imaginary values from the first plurality of real and imaginary values with corresponding imaginary values from the second plurality of real and imaginary values to generate a second plurality of real products; and addition/subtraction circuitry to subtract each real product in the second plurality of real products from a corresponding real product in the first plurality of real products to produce a corresponding real value in the result matrix. The decoder may also decode and the execution circuitry may execute a second complex matrix multiplication instruction to multiply real and imaginary values from the first plurality with corresponding imaginary and real values, respectively, from the second plurality to generate first and second pluralities of imaginary products, and to add corresponding imaginary products to produce a corresponding imaginary value in the result matrix.

Apparatus and method for complex matrix multiplication

An apparatus and method for complex matrix transpose and multiply. For example, one embodiment of a processor comprises: a decoder to decode a first complex matrix multiplication and transpose instruction including a first source operand to identify a first plurality of real and imaginary values in a first complex source matrix, a second source operand to identify a second plurality of real and imaginary values in a second complex source matrix, and a first destination operand to identify a result matrix with real and imaginary values; execution circuitry to execute the first complex matrix transpose and multiplication instruction, the execution circuitry comprising transpose hardware logic to transpose at least one of the source matrices, parallel multiplication circuitry to multiply real values from the first plurality of real and imaginary values with corresponding real values from the second plurality of real and imaginary values to generate a first plurality of real products, to multiply imaginary values from the first plurality of real and imaginary values with corresponding imaginary values from the second plurality of real and imaginary values to generate a second plurality of real products; and addition/subtraction circuitry to subtract each real product in the second plurality of real products from a corresponding real product in the first plurality of real products to produce a corresponding real value in the result matrix.

Apparatus and method for complex matrix transpose and multiply

Systems, methods, and apparatuses relating to interleaving data values. An embodiment includes decoding circuitry to decode a single instruction, the instruction having one or more fields to specify an opcode, one or more fields to specify a location of a first source operand, one or more fields to specify a location of a second source operand, one or more fields to specify a location of a destination operand, and one or more fields to specify an index value to be used to index a row in the first source operand, wherein the opcode is to indicate execution circuitry is to downconvert data elements of the indexed row of the first source operand, interleave the downconverted elements with data elements of the second source operand, and store the interleaved elements in the destination operand; and execution circuitry to execute the decoded instruction according to the opcode.

Apparatuses, methods, and systems for instructions for downconverting a tile row and interleaving with a register

Systems, methods, and apparatuses relating to a sign modification field for fused operations in a configurable spatial accelerator are described. In one embodiment, a hardware accelerator includes a plurality of processing elements; a network between the plurality of processing elements to transfer values between the plurality of processing elements; and a processing element of the plurality of processing elements comprising: a first plurality of input queues having a multiple bit width coupled to the network, at least one first output queue having the multiple bit width coupled to the network, operation circuitry coupled to the first plurality of input queues having the multiple bit width, a sign modification circuit coupled to the first plurality of input queues having the multiple bit width, and a configuration register within the processing element to store a configuration value comprising a sign modification field that causes the sign modification circuit to modify a sign bit of a value from the first plurality of input queues according to the sign modification field to create a sign modified value, and the configuration value causes the operation circuitry to perform a selected operation of a plurality of operations on a value from the first plurality of input queues and the sign modified value to create a resultant value, and store the resultant value in the at least one first output queue.

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Bath, United Kingdom

Daniel Towner