Motorola Corporation

Freescale Semiconductor,inc.

Daniel Thanh-Khac Pham

Bich-Yen Nguyen

Kimberly Gay Reid

Marc A Rossow

James P Geren

Anne Vandooren

Leo Mathew

Robert F Steimle

James Kenyon Schaeffer, Iii

Yeong-Jyh Tom Lii

Kuntal Joardar

Melissa O Zavala

Sherry G Straub

Al T Koh

Ricardo Garcia

Yaohui Zhang

A method for providing gates of transistors with at least two different work functions utilizes a silicidation of two different metals at different times, silicidation for one gate and polysilicon for the other, or silicidation using a single metal with two differently doped silicon structures. Thus the problem associated with performing silicidation of two different metals at the same time is avoided. If the two metals have significantly different silicidation temperatures, the one with the lower temperature silicidation will likely have significantly degraded performance as a result of having to also experience the higher temperature required to achieve silicidation with the other metal.

Method for forming a semiconductor device structure a semiconductor layer

A semiconductor fabrication process and structure in which a dielectric structure ( ) is formed upon a substrate ( ). Silicon is then deposited and processed to form a crystalline silicon wall ( ) that envelopes the dielectric structure ( ) and is physically and electrically isolated from the substrate ( ). A gate dielectric film ( ) is formed over at least two surfaces of the silicon wall ( ) and a gate electrode film ( ) is formed over the gate dielectric ( ). The gate electrode film ( ) is then patterned followed by conventional source/drain implant processing. Portions of the silicon wall ( ) disposed on either side of the gate electrode ( ) may then be contacted to form source/drain structures ( ). In this manner, the portion of the silicon wall ( ) covered by the gate electrode ( ) comprises a transistor channel region having multiple surfaces controlled by gate electrode ( ).

Multiple gate transistor employing monocrystalline silicon walls

Method for forming a semiconductor device structure in a semiconductor layer

A grooved channel Schottky contacted MOSFET has asymmetric source and drain regions. The MOSFET includes an undoped silicon substrate with a background doping concentration of less than about 10 cm . A grooved channel is formed in a first surface of the substrate. A first metal silicide material is formed in a first side of the grooved channel, forming a source region, and a second metal silicide material is formed on a second side of the grooved channel, forming a drain region. A metal gate is formed in the grooved channel. The grooved structure allows the off-state current to be reduced to less than 50 pA/&mgr;m. Further, the feature size can be scaled down to 10 nm without strong short-channel effects (DIBL<0.063) and the gate delay (CV/I) is reduced to 2.4 ps.

Grooved channel schottky MOSFET

Growing community of inventors

Austin, TX, United States of America

Daniel Thanh-Khac Pham