Digital Equipment Corporation

Analog and Digital Systems, Inc.

Daniel T Sullivan

James F O'Loughlin

Charles H Kaman

Richard Franklin Lary

Robert A Giggi

Jega A Arulpragasam

Craig Mudge

Richard E DeFreitas

Jamshed R Kapadia

George E Hitz

Variably delaying an audio signal by storing digital representions of the audio signal at sequential memory locations prescribed by an encoding pointer operating at one clock rate, and reading from the memory at sequential locations prescribed by a decoding pointer operating at the same or a different clock rate, with the difference in clock rates between the pointers prescribing the rate of change of delay. A memory addressing system in which a processor specifies the high-order portion of a memory address and a separate counter, clocked at a much higher rate than the processor, provides the low-order portion of the address.

Audio delay system

Generating clock signals of slightly different frequencies without the signals locking up in synchrony, by providing a voltage-to-frequency converter driven by the output of an integrator, which is supplied with a signal representative of the sum of a frequency-difference command and the difference in frequency between the two clocks.

Generating narrowly-separated variable-frequency clock signals

A multiprocessor data processing system, the processors (30) and input/output devices (32) of which share a common control unit (CCU 10) that includes a write-through cache memory (20), a memory management circuit (22) and an address translation circuit (24). The data processing system further includes random access memory (28) and a secondary storage facility (40, 42, 68, 70). The processors (30) and the input/output devices (32) use the memory management circuit (22), the address translation circuit (24) and the cache memory (20) in an ordered pipelined sequence. When a read command 'misses' the cache memory (20), the CCU accesses the memory modules (28) for allocating its cache memory (20) and for returning read data to the processors (30) or input/output devices (32). The CCU also includes a duplicate tag store (67) that maintains a copy of the cache memory address tag store (20A) thereby to enable the CCU to update its cache memory when data is written into a memory location that is to be maintained in the cache memory.

Cached multiprocessor system with pipeline timing

A cached multiprocessor system operates in an ordered pipeline timing sequence in which the time slot for use of the cache is made long enough to permit only one cache access. Further, the time slot for data transfers to and from the processors succeeds the time slot for accessing the cache. The sequence is optimized for transactions that require only one cache access, e.g., read operations that hit the cache. Transactions that require two cache accesses must complete the second cache access during a later available pipeline sequence. A processor indexed random access memory specifies when any given processor has a write operation outstanding for a location in the cache. This prevents the processor from reading the location before the write operation is completed.

Relating to cached multiprocessor system with pipeline timing

A processor in a data processing system comprising a plurality of units for performing various functions and at least one data bus interconnecting the units for transferring information therebetween. The processor also includes a control store for storing microprogrammed instructions which are directly coupled to the units of the processor for controlling the operation thereof. Certain ones of the microprogrammed processor instructions, which are utilized in the transfer of information between the units of the processor by means of the data bus, are also stored in a secondary control store whose contents are decoded by logic circuitry within the units of the processor which, in response thereto, couple the desired apparatus within the units to the data bus.

Processor for a data processing system

A writeable control store for storing a plurality of instructions used to control the operation of a processor in a data processing system. The control store may be utilized in a first mode wherein the instructions are accessed for controlling the operation of the processor and in a second mode wherein data is transferred to or retrieved from the control store. In the second mode of operation, a secondary control means is utilized to control the operation of the data transfers to and from the writeable control store.

Writeable control store for use in a data processing system

A data processing system is described herein having a central processor unit which responds to a plurality of diverse instructions including a diagnostic instruction. The diagnostic instruction is comprised of a first and second portion preferably in the form of distinct words which are separately transmitted to the processor from a peripheral storage location or manually transmitted from a control panel for the data processing system. The first word of the instruction, when decoded by the processor, identifies the diagnostic instruction and the second word specifies the particular function to be performed. The processor is arranged such that, in the response to the first word of instruction, the second word is coupled to a specialized decoding circuit which will generate a starting address in the microprogrammable control store of the processor for a routine to execute the function specified by the second word. Utilization of the diagnostic instruction in conjunction with other instructions for moving data to or reading data from an addressable storage register within the processor permits numerous diagnostic and testing functions to be performed such as, for example, the reading and writing of internal state registers which are not addressable at the programmer's level; the executing of selected portions of the microcode in the microprogrammable control store and the operation of the cache memory.

Growing community of inventors

Bolton, MA, United States of America

Daniel T Sullivan