Motorola Corporation

Amazon Technologies, Inc.

Daniel T Marquette

Christopher Neal Hinds

Eric E Quintana

Anthony Nicholas Liguori

Mark Bradley Davis

Alfred Larry Crouch

Grady L Giles

Matthew D Pressly

Eric V Fiene

Michael Alan Mateja

Clark Gilson Shepard

Asif Kahn

Jack Wu

Jason E Doege

Lee Allen Corley

Odis Dale Amason, Jr

A system that provides virtualized computing resources may include an enhanced PCIe endpoint device on which an emulation processor emulates PCIe compliant hardware in software. The endpoint device may include host interface circuitry that implements pointer registers and control and status registers for each of multiple transaction ring buffers instantiated in memory on the device. In response to receiving a transaction layer packet that includes a transaction, packet steering circuitry may push the transaction into one of the buffers, dependent on the transaction type, a routing identifier for an emulated device to which it is directed, its traffic class or other criteria. The transaction may be processed in software, emulating the hardware device. The host interface circuitry may generate response completion packets for configuration requests and non-posted transactions, and may return them according to PCIe ordering rules, regardless of the order in which they were processed on the endpoint device.

Hardware acceleration for software emulation of PCI express compliant devices

A method and implementation for providing an improved testable design for an integrated circuit (IC) device. The integrated circuit includes a functional path for the implementation of a functional specification as well as a testing path for testing the timing specifications for the integrated circuit. Input switching devices are connected between input terminals of the IC and inputs to sequential circuit elements, for example flip-flop devices, in the IC. Similarly, output switching devices are connected between outputs of the flip-flop devices and output terminals of the IC. The switching devices are selectively operable to alternately connect the flip-flop devices into either a functional IC path for providing functional output signals during functional cycles, or into a testing IC path for providing testing output signals indicative of timing points throughout the IC during testing cycles. The IC is also operable to selectively disable tristate bus drivers during the testing cycles. The switching devices are arranged such that a single output terminal of the IC may be selectively used to provide both functional and testing output signals.

Scan based testing of an integrated circuit for compliance with timing

A data processing system (10) has a circuit for determining floating point exponents for divide operations and square root operations. The circuit has two input multiplexers (26 and 28) which provide exponent information or constants to an adder (30). The exponent information and constants are processed by the adder (30) to output three possible exponent values for either a divide operation or a square root operation. The three possible exponent values are stored in three registers (34, 36, and 38). A multiplexer (40) used mantissa rounding and normalizing information to determine which exponent of the three possible exponent values are correct for the current floating point calculation.

Method and apparatus for calculating floating point exponent values

A zero detection method (FIG. 5) and a zero detection apparatus (FIGS. 2-4) involves determining if the sum of at least two operands and a carry-in bit will produce a zero result. The zero detection is performed in parallel to another system calculation, such as an addition or subtraction of the two operands. The zero detection logic has a hierarchical structure (see FIG. 4) which is used to reduce logic and quicken the zero detect process of FIG. 5. Zero detection may occur for more than one group of bits within the two operands. The zero detection is used, in a preferred form, primarily in floating point operations such as floating point additions.

Method and apparatus for performing parallel zero detection in a data

A method and apparatus for detecting and completing floating point operations involving special floating point operands is performed in parallel, via a circuit (24), to the operation of at least one floating point mathematical unit (18, 20or 22). The floating point control (30) along with registers (14 and 16) provide floating point operands and floating point control to the mathematical units (18, 20, and 22). If the mathematical units (18, 20, and 22) cannot perform a proper floating point calculation because of the presence of a special operand, then the circuit (24) will detect the special operand and complete the floating point operation in a proper manner by communicating with the floating point control unit (30).

Parallel method and apparatus for detecting and completing floating

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Austin, TX, United States of America

Daniel T Marquette