Seagate Technology Incorporated

Daniel Sullivan

Andrew D Habermas

Sangho Kim

Joseph Michael Stephan

Daniel Richard Buettner

Dongsung Hong

Lily Horng Youtt

Lijuan Zou

Carolyn Pitcher Van Dorn

The present disclosure includes methods of forming air bearing surfaces having multi-tier structures using nanoimprint technology and/or 3D printing technology. In some embodiments, a single stage of milling can be used to transfer a multi-tier photoresist pattern into a substrate (e.g., an AlTiC substrate).

Slider having angled or curvilinear sidewalls

Methods of forming an air bearing surface on a slider and related sliders

The formation of substrate electrical connections on thin film heads is one source of resulting surface topography. In accordance with one implementation, such topography can be reduced by a process that includes depositing a first layer of basecoat, creating electrical recessed vias in one or more plating processes, and depositing a second layer of basecoat on top of the electrical vias and on top of the first layer of basecoat. In one implementation, the first and second layers of basecoat have a combined height that is substantially equal to the height of the electrical recessed vias. In one implementation, the resulting topographical features are small enough that they can be planarized without creating a lack of uniformity in the total basecoat thickness across the wafer.

Electrical connection with reduced topography

When opaque films are deposited on semi-conductor wafers, underlying alignment marks may be concealed. The re-exposure of such alignment marks is one source of resulting surface topography. In accordance with one implementation, alignment marks embedded in a wafer may be exposed by removing material from one or more layers and by replacing such material with a transparent material. In accordance with another implementation, the amount of material removed in an alignment mark recovery process may be mitigated by selectively ashing or etching above a stop layer.

Alignment mark recovery with reduced topography

Nanoimprint lithography can be used in a variety of ways to improve resolution, pattern fidelity and symmetry of microelectronic structures for thin film head manufacturing. For example, write poles, readers, and near-field transducers can be manufactured with tighter tolerances that improve the performance of the microelectronic structures. Further, entire bars of thin film heads can be manufactured simultaneously using nanoimprint lithography, which reduces or eliminated alignment errors between neighboring thin film heads in a bar of thin film heads.

Nanoimprint lithography for thin film heads

First and second anchor features are formed on a photolithography mask, each having a respective center point. An elongated, chromeless, bridging feature is formed between the anchor features. The bridging feature is offset from the center points of the anchor feature to minimize distortions of a corresponding photoresist feature formed by the bridging feature.

Forming a bridging feature using chromeless phase-shift lithography

First and second anchor features are formed on a substrate via a chromeless photolithography process. An elongated bridging feature is formed between the anchor features on the substrate via the chromeless photolithography process. A distance between the anchor features is sufficient to minimize lateral displacement at a center portion of the bridging feature without significant reduction in mechanical stability of the bridging feature.

An elongated, chromeless, bridging feature is formed on a photolithography mask with an etching depth that causes a nominal phase difference of more than 180 degrees to energy passing through the photolithography mask. A corresponding photoresist feature is formed using the bridging feature. The phase difference may be chosen to minimize dimensional variation of the corresponding photoresist feature.

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Carver, MN, United States of America

Daniel Sullivan