Intel Corporation

Daniel Sira

Domagoj Siprak

Stephan Leuschner

Gerhard Knoblinger

Michael Fulde

Jonas Fritzin

An integrated circuit structure includes a first metallization layer with first and second electrodes, each of which has electrode fingers. A second metallization layer may be included below the first metallization layer and include one or more electrodes with electrode fingers. The integrated circuit structure is configured to exhibit at least partial vertical inductance cancellation when the first electrode and second electrode are energized. The integrated circuit structure can be configured to also exhibit horizontal inductance cancellation between adjacent electrode fingers. Also disclosed is a simulation model that includes a capacitor model that models capacitance between electrode fingers having a finger length and includes at least one resistor-capacitor series circuit in which a resistance of the resistor increases with decreasing finger length for at least some values of the finger length.

High frequency capacitor with inductance cancellation

An apparatus for a network matching switch is provided. The apparatus includes a primary winding, a first secondary winding, a second secondary winding and a plurality of matching network paths. The primary winding is configured to generate a magnetic field based on an analog input signal. The first secondary winding is configured is inductively coupled to the primary winding. The second secondary winding is inductively coupled to the primary winding. The plurality of matching network paths are coupled to the first secondary winding and the second secondary winding. An active path is selected from the plurality of matching network paths and provides power to an active load.

Transmitter matching network using a transformer

A digital-to-analog converter circuit including a plurality of digital-to-analog converter cells is provided. A first digital-to-analog converter cell of the plurality of digital-to-analog converter cells includes a cell control module configured to provide alternatingly a first voltage and a second voltage to a first electrode of a capacitive element of the first digital-to-analog converter cell based on a digital input signal during a predefined time interval. A second digital-to-analog converter cell of the plurality of digital-to-analog converter cells includes a cell control module configured to provide a third voltage to a first electrode of a capacitive element of the second digital-to-analog converter cell during the predefined time interval. The first voltage is higher than an upper threshold voltage corresponding to a first digital threshold level of the digital input signal and the second voltage is lower than a lower threshold voltage corresponding to a second digital threshold level of the digital input signal. The third voltage is constantly between the upper threshold voltage and the lower threshold voltage.

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Munich, Germany

Daniel Sira