International Business Machines Corporation

Nova Corporation

Daniel Schmidt

Alexander Reznicek

Ruilong Xie

Tsung-Sheng Kang

Dexin Kong

Ekmini Anuja De Silva

Ashim Dutta

Igor Turovets

Aron Cepler

Marjorie Cheng

Roy Koret

Embodiments are disclosed for a method for fabricating a semiconductor device. The method includes forming a recess under a region for a source/drain (S/D). The method further includes depositing a sacrificial placeholder liner conformally. Additionally, the method includes performing a sacrificial material overfill. Further, the method includes performing an etch back of the sacrificial material overfill. Also, the method includes performing S/D epitaxial (epi) growth over a remaining placeholder sacrificial liner to generate an S/D epi for the S/D.

Semiconductor device with void under source/drain region for backside contact

A semiconductor device includes a nanosheet stack on a substrate. A first source/drain is on a first side of the nanosheet stack and a second source/drain is on an opposing side of the nanosheet stack. A backside contact includes a first contact end on a first end of the first source/drain and an opposing second contact end in electrical communication with a backside power distribution network. A frontside contact includes a first contact end on a first end of the second source/drain and an opposing second contact end in electrical communication with a backend of line (BEOL) interconnect. A placeholder extends from an opposing second end of the second source/drain.

Epi growth uniformity with source/drain placeholder

A method of characterizing asymmetric depositions on a target is provided. The method includes forming at least four asymmetrical petals in a layer on a substrate, and depositing a light-absorbing material on the at least four asymmetrical petals, wherein the light-absorbing material deposits unevenly on a plurality of walls of the at least four asymmetrical petals. The method further includes determining a pattern shift response (PSR) from the light-absorbing material on each of the walls of the at least four asymmetrical petals, and converting the pattern shift response (PSR) to an asymmetry of thicknesses of the light-absorbing material deposited on facing walls of the at least four asymmetrical petals. The method further includes correcting an overlay petal position based on the asymmetry of thicknesses.

Characterization of asymmetric material deposition for metrology

A stacked field effect transistor (stacked-FET) device includes a first layer comprising at least one first layer transistor structure comprising a plurality of first layer terminals, a diffusion break dielectric fill region adjacent to one of the first layer terminals, a second layer overlying and adjacent to the first layer and comprising at least one second layer transistor structure comprising a plurality of second layer terminals, and a contact wiring between the first layer and the second layer passing through the diffusion break dielectric fill region of the first layer and connecting with one of the second layer terminals.

Diffusion-break region in stacked-FET integrated circuit device

Embodiments of present invention provide a method of forming a semiconductor structure. The method includes forming a first set of nanosheets and a second set of nanosheets on top of the first set of nanosheets, wherein the first set of nanosheets has an uppermost nanosheet and the second set of nanosheets has a lowermost nanosheet, the lowermost nanosheet being separated from the uppermost nanosheet by a first gap; forming a conformal liner covering the first set of nanosheets and the first gap; covering a first portion of the conformal liner at the first gap with a protective stud; selectively removing a second portion of the conformal liner from end surfaces of the first set of nanosheets; and forming source/drain at the end surfaces of the first set of nanosheets. A structure formed thereby is also provided.

Source/drain epitaxy process in stacked FET

A method, a system, and a non-transitory computer readable medium for measuring a local critical dimension uniformity of an array of two-dimensional structural elements, the method may include obtaining an acquired optical spectrometry spectrum of the array; feeding the acquired optical spectrometry spectrum of the array to a trained machine learning process, wherein the trained machine learning process is trained to map an optical spectrometry spectrum to an average critical dimension (CD) and a local critical dimension uniformity (LCDU); and outputting, by the trained machine learning process, the average CD and the LCDU of the array.

Measuring local CD uniformity using scatterometry and machine learning

A computer-implemented method of using a control module to control a lithographic apparatus includes pre-calculating, using a processor, a library of pupil images for a measuring spot of an object-under-test, wherein each pupil image represents a simulated structure of the object-under-test at the measuring spot given a particular set of configuration values and a particular probing wavelength used for testing the object-under-test using scatterometry. The method further includes, in response to receiving a real-time pupil image when testing the object-under-test using scatterometry, comparing, using the processor, the real-time pupil image with the library of pupil images to identify a best match from the library. The method further includes outputting a set of configuration values associated with the best match from the library.

Metrology data correction

A high-density resistive random-access memory array with self-aligned bottom electrode contact includes a plurality of electrically conductive structures embedded in an interconnect dielectric material layer, a bottom electrode selectively grown over, and electrically connected to, each of the electrically conductive structures with the bottom electrode above an electrically conductive structure being separated from the bottom electrode above another electrically conductive structure by a first dielectric filling layer, the bottom electrode having a semi-circular shape. The array further includes a resistive random-access memory pillar disposed above the bottom electrode.

High-density resistive random-access memory array with self-aligned bottom electrode contact

A memory device is provided. The memory device includes a memory stack on a first dielectric layer, and a sidewall spacer on the memory stack. The memory device further includes a conductive cap on the sidewall spacer and the memory stack and an upper metal line on the conductive cap and the sidewall spacer, wherein the upper metal line wraps around the conductive cap, sidewall spacer, and memory stack.

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Niskayuna, NY, United States of America

Daniel Schmidt