Infineon Technologies Ag

Daniel Schleisser

Dirk Ahlers

Thomas Stoek

Gilles Delarozee

Christopher Spielman

Frank Daeche

A semiconductor arrangement comprises a leadframe comprising at least a first and a second carrier, the first and second carriers being arranged laterally besides each other, at least a first and a second semiconductor die, the first semiconductor die being arranged on and electrically coupled to the first carrier and the second semiconductor die being arranged on and electrically coupled to the second carrier, and an interconnection configured to mechanically fix the first carrier to the second carrier and to electrically insulate the first carrier from the second carrier, wherein the first and second semiconductor dies are at least partially exposed to the outside.

Semiconductor arrangement, laminated semiconductor arrangement and method for fabricating a semiconductor arrangement

A semiconductor package includes a leadframe, a first transistor chip connected to a first island of the leadframe in a drain-down configuration, and a second transistor chip connected to a second island of the leadframe in the same drain-down configuration as the first transistor chip. The first and the second islands of the leadframe are mutually electrically isolated from one another. The first island includes an extension which extends beyond a perimeter of the first transistor chip in a direction towards the second island and overlaps the second transistor chip. The first transistor chip and the second transistor chip are electrically interconnected with one another via the extension of the first island and a first electric connection element electrically connecting the extension to the second transistor chip to form a half bridge circuit.

Semiconductor package with leadframe

A package comprising an at least partially electrically conductive chip carrier, a first transistor chip comprising a first connection terminal, a second connection terminal and a control terminal, and a second transistor chip comprising a first connection terminal, a second connection terminal and a control terminal, wherein the first transistor chip and the second transistor chip are connected to form a half bridge, and wherein the second connection terminal of the first transistor chip is electrically coupled with the first connection terminal of the second transistor chip by a bar section of the chip carrier extending between an exterior edge region of the first transistor chip and an exterior edge region of the second transistor chip and maintaining a gap laterally spacing the first transistor chip with regard to the second transistor chip.

Growing community of inventors

Munich, Germany

Daniel Schleisser