Samsung Electronics Co., Ltd.

Other

Samsung Austin Semiconductor, LP

Daniel Sawyer

Ki-Don Lee

Xiaoming Chen

Pedro Morrison

Steven English

Maihan Nguyen

Osamu Arasaki

Tammy Maraquin

An interconnect structure and a method to form an interconnect structure utilizes a high-aspect ratio single-damascene line and a non-damascene via. The interconnect includes a first single-damascene interconnect line disposed in a first interlayer dielectric layer, and a non-damascene via on the first single-damascene interconnect line that may be formed from cobalt, titanium and/or tungsten. A first SiCN layer may be formed on one or more sidewalls of the non-damascene via. A second single-damascene layer may be formed on the non-damascene via in which the second single-damascene layer may be disposed in a second interlayer dielectric layer. A second SiCN layer may be formed on at least part of an upper surface of the first single-damascene layer, and a third SiCN layer may be formed on at least part of an upper surface of the second single-damascene layer.

Interconnect structure formed with a high aspect ratio single damascene copper line on a non-damascene via

One embodiment of an improved method for removing a post from the ground, the method including inserting a spike tool into the ground around the perimeter of the base of the post, reducing the lifting force required by creating a layer of reduced friction mud surrounding the base of the post, supplying of pressurized fluid through the spike tool to the base of the post within the ground, and neutralizing the suction force created when the post is lifted from the ground.

Method for post removal including concrete footing removal

A method for haze control on a semiconductor reticle, the method including performing a reticle inspection of a semiconductor reticle to detect haze formation on a periodic basis, performing a wafer inspection to detect haze defects, forecasting haze formation, and cleaning the semiconductor reticle. Also included is a haze forecasting method for haze control on a semiconductor reticle, including scanning a plurality of semiconductor wafers, identifying repeating defects in the semiconductor wafers, storing the repeating defects in a database as known repeating defects, and identifying an additional repeating defect that is not a known repeating defect, the additional repeating defect caused by semiconductor reticle haze.

System and method for haze control in semiconductor processes

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Pflugerville, TX, United States of America

Daniel Sawyer