Alcatel N.v.

Daniel Sallaerts

Joannes M Sevenhans

Peter P Reusens

Pierre-Paul F Guebels

Leon Cloetens

Jurgen M Tombal

Eric Duvivier

Michel C Rahier

Jacques Wenin

Rudolf F Dierckx

Arnoul O Vanwelsenaers

A tunable quadrature phase shifter including two branches each constituted by the cascade connection of a filter, an amplifier and a summing circuit, and two cross-connections constituted by amplifiers interconnecting the filter of one branch to the summing circuit of the opposite branch. An accurate 90 degrees phase shift between the two output signals is obtained by controlling the tail currents of the four amplifiers. The phase shifter used in mobile telecommunication transceivers may be easily and accurately tuned because the signals used in the summing circuits all have a similar amplitude. It is further adapted to operate with only a 3 Volt battery supply as used in wireless phones. The bandwidth of the amplifiers is increased by using double differential pair amplifiers which behave as cascode arrangements.

Differential amplifier having a double differential amplifier pair with

A data, synchronization device adapted to re-synchronize a multi-level digital signal (IN; OUT) with an output or local clock signal (CLKO). In case of a binary signal, the device includes two counter systems (CA1-CC1, MAJ1, SEL1; CA0-CC0, MAJ0, SEL0) each associated with a logical level of the signal and counting the number of successive 1's or 0's respectively. These counter systems produce a count number including the number of counted bits and their level. The device further includes a decoder (DEC) generating in synchronism with the local clock signal (CLKO) a number of bits which is a function of the count numbers. These generated bits constitute the requested output signal (OUT). The data synchronization device further includes delay module (DEL) for deriving from an input clock signal (CLKI) received with the input signal (IN), three intermediate clock signals (OA-OC) shifted in phase with respect to each other and each controlling one of a set of three counters (CA1-CC1; CA0-CC0) included in each of the counter systems. The latter also each include a majority voting module (MAJ1; MAJ0) reading the numbers of bits counted by the three counters of the corresponding set, comparing these numbers and selecting the subset of at least two counters having counted a same number of bits. The number of bits counted by the majority of the set counters is assumed to be correct and is therefore transferred to the decoder (DEC).

Data synchronization device

A level converts circuit converting a digital input signal varying between a first (VSS) and a second (VDD1) voltage level to a digital output signal varying between the first (VSS) and a third voltage. (VDD2) the local conversion circuit includes between first (VDD2) and second (VSS) poles of a DC supply source a series connection of a load impedance (P2/P3/N3) and the main paths of a first transistor (N2) and of a second transistor (N1), to a control electrode of which the input signal is applied. The first and second transistor are of a same first conductivity type. A third transistor (P1) of a second conductivity type is connected in parallel with the second transistor (N1). A control electrode of the third (P1) and first (N2) transistors are biased by a constant DC bias voltage (VBIAS1A/VBIAS1B), and a junction point of the load impedance (P2/P3/N3) and the series connection being an output terminal (OUT) of the level conversion circuit.

Level conversion circuits for converting a digital input signal varying

The direct conversion receiver DCR receives analog modulating signals with a reference average value and modulated within assigned time slots of a TDMA-structure on a carrier with a carrier frequency FC which changes from time slot to time slot. DCR includes a demodulator circuit DC-coupled to a baseband circuit, the demodulator circuit including a local oscillator LO and a mixer MIX and the baseband circuit including an offset correction circuit OCC/OCC' for updating different variable parameter offset correction values for different FC stored in a memory MEM and compensating offset introduced in DCR. OCC/OCC' determines, upon occurrence of an assigned time slot, an updated offset correction value as a function of an old offset correction value in a corresponding storage location of MEM and the difference between an average value of the analog signal and the reference average value, and thereupon stores the result in the corresponding storage place.

Offset correction circuit

A data transmission system is proposed in which an auxiliary bitstream of low bitrate (AUX) is coded together with a main bitstream of high bitrate (PRIM) without increasing the transmission rate above the high bitrate. This auxiliary bitstream (AUX) is moreover transmitted synchronously with the main bitstream (PRIM). Transmitter (T) divides the main bitstream (PRIM) in periodically occurring blocks of Y bits and codes one bit of the auxiliary bitstream (AUX) in each of the blocks by using a first (AMI) or a second (VAMI) coding law according to the binary value of that bit. The second law is constructed by violating the first coding law (AMI) according to a predetermined violation law. Redundancy in the first coding law (AMI) is used to introduce symbol sequences not permitted under this first coding law (AMI) and to so obtain the second coding law (VAMI).

Data transmission system for synchronously transmitting an auxiliary

A signal persistence time interval recognition system reproduces a condition of an input signal as a condition of an output signal only when the input signal condition persists for at least a predetermined time interval. The system periodically scans the input signal condition and has a first memory (ROM) for storing a start value indicative of the time interval. A second memory (RAM) stores a value indicative of the time counted since the detection of a difference between the input and output signal conditions. A third memory stores the output signal condition and a processor brings the start value from the first memory into the second memory when no difference is detected. The processor modifies the value in the second memory each time such a difference is detected and until a value is reached indicating that the time interval has been counted, the output signal condition in the third memory being then changed. The first memory only stores a single start value for all conditions of the input signal and the processor perform the modification in the second memory independently of the first memory.

Signal recognition system

An echo canceller, using an Adaptive Finite Input Response Filter (AFIR), uses a processing device with a plurality of interconnected cells. These cells, connected in a systolic arrangement, determines the function of three variables m, n, and p, in the equation p+m n, where m and n are data inputs to each of the cells, and p is the output of a previous calculation cell. This is achieved by using a timing sequence, in which the variable m is applied bit serial to the cells over a period of q time slots, and the variable n is applied in parallel over the cells in one time slot.

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Aarschot, Belgium

Daniel Sallaerts