Sun Microsystems, Inc.

Daniel S Rice

Ashley N Saulsbury

Michael Frank Deering

Michael W Parkin

Michael G Lavelle

Stephen K Howell

Peter Farkas

Chang-Guo Zhou

Yajyun Wang

Douglas C Twilleager

Texture mapping includes (i) calculating the weighted average of the colors of two texels near a particular pixel, (ii) determining a fractional portion of a texture coordinate of the pixel, and (iii) retrieval of a pair of complementary coefficients from a table of pairs of predetermined, complementary coefficients according to the fractional portion of the coordinate of the pixel. Each of the complementary coefficients corresponds to the relative distance between the pixel and each of the two texels as represented by the fractional portion of the first coordinate of the pixel in the coordinate space of the texture image since each texel has whole, integer coordinates in the coordinate space of the texture image. Each coefficient of the pair of complementary coefficients is used to weight a respective one of the colors of the two texels and the weighted colors are summed to produce a weighted average color of the two texels. A weighted average of the colors of the other two of the four nearest texels is calculated in the same manner. The pair of complementary coefficients are partitioned values in a single data word and are therefore loaded into the processor which performs the calculate the weighted average only once to weight two separate colors. The precision and data format of each coefficient of the table are the same as the precision and data format of each component of each pixel of the rendered graphical image. Accordingly, the processing environment remains unchanged while a computer processor alternately interpolates a texel color and combines the interpolated texel color with the color of the pixel.

Texture mapping method and apparatus for computer implemented graphical image processing

According to the invention, a process for averaging two pixel values is disclosed. In one step, an instruction is decoded. A plurality of first operands is loaded from a first input register. A plurality of second operands is loaded from a second input register. An average of one of the plurality of first operands and one of the plurality of second operands is produced. The average is stored in an output register.

Methods and apparatus for performing pixel average operations

A processing pipeline and method are disclosed that may enable real time video rate displacement mapping. The pipeline may include one or more: render units, texture units, memories, and displacement units. Render units may tessellate a geometric primitive into micropolygons and interpolate parameter values for each new vertex. The micropolygons may be defined by the intersection of the geometric primitive and boundaries projected from specified screen space regions. Texture units retrieve displacement values from a displacement map stored in memory. Displacement units displace each vertex of a micropolygon in the direction of the normal at each vertex by a distance based on the displacement value determined for the vertex location. Micropolygons that are displaced across a projected boundary may be returned to the render units and re-tessellated according to the projected boundaries. Parameter values for new vertices may be determined subject to an edge contract to prevent surface cracks.

Displacement mapping by using two passes through the same rasterizer

According to the invention, a processing core is disclosed that includes a first source register, a number of second operands, a destination register, and a number of arithmetic processors. A bitwise inverter is coupled to at least one of the first number of operands and the second number of operands. The first source register includes a plurality of first operands and the destination register includes a plurality of results. The number of arithmetic processors are respectively coupled to the first operands, second operands and results, wherein each arithmetic processor computes one of a sum and a difference of the first operand and a respective second operand.

Processing architecture having parallel arithmetic capability

A graphical processing system comprising a computational unit and a shadow processing unit coupled to the computational unit through a communication bus. The computational unit is configured to transfer coordinates Cof a point P with respect to a first space to the shadow processing unit. In response to receiving the coordinates C, the shadow processing unit is configured to: (a) transform the coordinate Cto determine map coordinates s and t and a depth value Dfor the point P, (b) access a neighborhood of depth values from a memory using the map coordinates s and t, (c) compare the depth value Dto the depth values of the neighborhood, (d) filter binary results of the comparisons to determine a shadow fraction, and (e) transfer the shadow fraction to the computational unit through the communication bus.

System and method for computing filtered shadow estimates using reduced bandwidth

A processing core comprising R-number of processing pipelines each comprising N-number of processing paths. Each of the R-number of processing pipelines are synchronized together to operate as a single very long instruction word (VLIW) processing core. The VLIW processing core is configured to process R&#xd7;N-number of VLIW sub-instructions in parallel. In addition, the R-number of pipelines can be configured to operate independently as separately operating pipelines. In accordance with one embodiment of the present invention, each of the R-number of processing pipelines comprises S-number of register files, such that the processing core comprises R&#xd7;S-number of register files. In accordance with another embodiment of the present invention, each of the R-number of processing pipelines comprises one register file for every two of the N-number of processing paths, such that S=N/2. In accordance with yet another embodiment of the invention, a single VLIW processing instruction comprises R&#xd7;N-number of P-bit sub-instructions appended together.

Computer processing architecture having a scalable number of processing paths and pipelines

According to the invention, a processing core is disclosed. The processing core includes one or more processing pipelines and a number of register flies. The processing pipelines having a total of N-number of processing paths, where each of the processing paths processes instructions on M-bit data words. Each of the number of register files has Q-number of registers that are each M-bits wide. The Q-number of registers within each of the plurality of register files are either private or global registers. When a value is written to one of said Q-number of said registers, which is a global register within one of said number of register files, the value is propagated to a corresponding global register in the other of the number of register files. When a value is written to one of said Q-number of the registers, which is a private register within one of said number of register files, the value is not propagated to a corresponding register in the other of said number of register files.

VLIW computer processing architecture having a scalable number of register files

According to the invention, a processing core that includes a first source register, a second source register, a multiplexer, a destination register, and an operand processor is disclosed. The first source register includes a plurality of source fields. The second source register includes a number of result field select values and a number of operation fields. The multiplexer is coupled to at least one of the source fields. Included in the destination register is a plurality of result fields. The operand processor and multiplexer operate upon at least one of the source fields.

Processing architecture having field swapping capability

A microprocessor with reduced context switching overhead and a corresponding method is disclosed. The microprocessor comprises a working register file that comprises dirty bit registers and working registers. The working registers including one or more corresponding working registers for each of the dirty bit registers. The microprocessor also comprises a decoder unit that is configured to decode an instruction that has a dirty bit register field specifying a selected dirty bit register of the dirty bit registers. The decoder unit is configured to generate decode signals in response. Furthermore, the working register file is configured to cause the selected dirty bit register to store a new dirty bit in response to the decode signals. The new dirty bit indicates that each operand stored by the one or more corresponding working registers is inactive and no longer needs to be saved to memory if a new context switch occurs.

Microprocessor with reduced context switching overhead and corresponding method

Mapping of pixels of a graphical object to a destination graphical image buffer is achieved by precalculating relative weights of object pixels near a subject pixel and storing the precalculated relative weights in a table and by determining weights of specific object pixels during processing by a table lookup of the predetermined weights according to a fractional portion of an object pixel address. A partitioned coefficient, which represents the relative weights of two or more object pixels, is retrieved from the weight table and used in a partitioned multiplication operation in a processor to weight each of the two or more object pixels substantially simultaneously. Weights associated with two or more object pixels are formed by partitioned multiplication of a partitioned horizontal weight word and a partitioned vertical weight word. The partitioned horizontal weight word is retrieved from a table of precalculated partitioned horizontal weight words according to fractional portion of a horizontal component of the object pixel address. Similarly, the partitioned vertical weight word is retrieved from a table of precalculated partitioned vertical weight words according to fractional portion of a vertical component of the object pixel address. In addition, partitioned processing operations are used to map multiple pixels of a graphical object to a destination graphical image buffer substantially simultaneously. Multiple partitioned data words, each of which represents multiple components of a respective mapped pixel, are transposed such that each partitioned data word includes a component of each of the mapped pixels and the transposed partitioned data words are summed in a partitioned addition operation. Accordingly, components of multiple mapped pixels are accumulated substantially simultaneously to form the multiple mapped pixels substantially simultaneously.

Graphical image mapping using partitioned operations

A number of multiple-band pixels are stored in a number of data words and the multiple-band pixels are merged and sorted such that all components of each band of the pixels are stored contiguously and in the order in which the multiple-band pixels are originally stored in the data words. As a result, the pixels are converted from an interleaved format to a planar format. The data words are essentially divided in half and the halves are merged such that the pixel components are interleaved in a number of intermediate data words. By repeatedly dividing the intermediate data words in half and merging the respective halves, the components of all the pixels corresponding to each band are stored contiguously in a number of data words. The contiguous components of each band are sorted such that the components of each band are stored in the order in which the multiple-band pixels are originally stored in the data words. For example, the contiguous components can be sorted using the same merge operation used to sift the components of the respective bands into contiguous storage locations.

Graphical image reformatting

A method and system for resizing images in a computer system. A plurality of buffers are dynamically created in the memory of the computer system. Among the created buffers are a horizontal sampling buffer and two vertical sampling buffers. The horizontal sampling buffer is filled with data from a plurality of rows of the source image. The horizontal sampling buffer is composed of sub-buffers, each constituting a subset of the horizontal sampling buffer. Each sub-buffer is bytewise transposed to provide easy access to different channels of the image data. A filter is then applied to the transposed data with a result being stored in another buffer. The filtered data is then retransposed to assume its original configuration. The retransposed data is stored in a vertical sampling buffer previously created. The foregoing steps are repeated to fill a second vertical sampling buffer. Thereafter throughout the processing, two vertical sampling buffers remain continuously filled to allow vertical filtering without concern for invalid data. When data is no longer needed in one of the vertical sampling buffers for the ongoing filtering, it can be refilled with new data corresponding to the next group of vertical neighbors. By buffering the data, various symmetries can be exploited and known problems such as edge conditions and alignment issues can be handled early in the resizing scheme providing for more efficient processor operation.

Method and apparatus for scaling images

A method of transposing data. Either eight bit or sixteen bit data is placed in a buffer. Each buffer is defined to contain one or more sub-buffers. Rows of the sub-buffer are selectively interleaved with the results of the selective interleaving being again interleaved in a specific order. Successive interleavings create the transpose of the original sub-buffer.

Method of transposing data buffer by selectively merging pairs of rows,

In a processor, a method for performing table-lookup transformation through a look-up table a source image having a plurality of source pixels to derive a destination image having a plurality of destination pixels. The method includes the step of deriving, for each value in a source pixel of the plurality of source pixels, a look-up result. The aforementioned look-up result represents a value in a corresponding destination pixel of the plurality of destination pixels. The method further includes the steps of loading a plurality of the look-up results into a plurality of graphics registers in the processor and accumulating the plurality of the look-up results in the plurality of graphics registers into an accumulation register in the processor. Additionally, there is also provided the step of storing the accumulation register into the destination image.

Methods and apparatus for table lookup transformation of digital images

A pixel of a color video image is converted from one color format having luminance and chrominance signals, e.g., YUV format, to a destination format, e.g., RGB or CMY formats, by forming luminance and chrominance component words which include partitioned words representing various color components of the luminance and chrominance signals. The luminance and chrominance component words are summed using a partitioned addition operation to thereby accumulate the various color components of the luminance and chrominance signals simultaneously and in parallel. Formation of the luminance and chrominance component words is, in some instances, done by a load and store unit of a central processing unit while a graphics execution unit simultaneously sums the luminance and chrominance components using the partitioned addition operation. By using this technique, conversion of pixels of a color motion image from YUV format to a different format, e.g., RGB format, is reduced from approximately 20 instruction cycles per pixel to generally less than 2.5 instruction cycles per pixel. Such a reduction in processing requirements has enabled full real-time rendering, e.g., thirty frames per second, of full-sized, digital NTSC, MPEG-compressed, motion video images using only a central processing unit and appropriately configured computer software. No additional, special-purpose hardware components were needed.

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Oakland, CA, United States of America

Daniel S Rice