Motorola Corporation

Tae Technologies, Inc.

Other

University of Texas System

Cube Technology, Inc.

Daniel S Marshall

Jerald A Hallmark

William J Ooms

Robert Michael Gardner

Ravindranath Droopad

Jun J Wang

Yang Wang

Jonathan K Abrokwah

Yi Wei

Zhiyi Jimmy Yu

William M Peterson

Hao Li

David J Anderson

Joseph W Bostaph

Yong Liang

Ellen Lan

Harland G Tompkins

Anatoly Muchnikov

Lucia R Salem

Glenn A Glass

Jean Anne Incorvia

Suyogya Karki

Sergey Vdovichev

Xiao M Hu

Passivation regions and device configurations are described herein. The passivation regions can be configured to seal against diffusion of an objective material from an underlying region into and/or through the passivation region. The passivation regions can also be configured to seal against diffusion of an externally sourced or ambient substance into and/or through the passivation region towards the underlying region.

Materials and configurations for protection of objective materials

A magnetic tunnel junction device is disclosed comprising a first device layer comprising a material having a magnetic moment; a second device layer comprising a material having a magnetic moment, e.g., wherein the magnetic moment of the material of the second device layer is different from that of the material of the first device layer; and a barrier layer, e.g., tunnel barrier, having a first interface to the first device layer comprising predominantly of a scandium nitride (ScN) material and having a second interface to the second device layer comprising predominantly of a scandium nitride (ScN) material.

Scandium nitride magnetic tunnel junction device

A magnetically polarized photonic device is provided. The magnetically polarized photonic device () includes substrate (), an annihilation layer () and a graded band gap layer (). The annihilation layer () is deposed on a surface () of substrate () with graded band gap layer () disposed on annihilation layer (). Contacts () are disposed on ends () of magnetically polarized photonic device (). A magnetic field () is applied to graded band gap layer () and annihilation layer () to drive charges to contacts ().

Magnetically polarized photonic device

A method of dispersing fine particles in a spray including the steps of providing a liquid carrier having a critical point and fine particles of at least one material. The fine particles are dispersed in the liquid carrier. A supercritical carrier containing dispersed particles is created by driving the liquid carrier containing dispersed fine particles above the critical point. The pressure of the supercritical carrier containing dispersed particles is reduced thereby forming a vapor carrier containing dispersed particles therein. The vapor carrier containing dispersed fine particles is then discharged.

Method of dispersing fine particles in a spray

A combustor includes a combustor head with an integrated counter-flow heat exchanger. The combustor head defines a combustion chamber and has a surface accessible for external delivery of thermal energy. The counter-flow heat exchanger has a fuel channel extending between a fuel inlet and a fuel outlet coupled to the combustion chamber, an exhaust channel extending between an exhaust inlet coupled to the combustion chamber and an exhaust outlet, and a shared wall between the fuel channel and the exhaust channel for transfer of thermal energy therebetween.

Combustor with integrated counter-flow heat exchanger

High quality monocrystalline metal oxide layers are grown on a monocrystalline substrate such as a silicon wafer. The monocrystalline metal oxide is grown on the silicon substrate at a temperature low enough to prevent deleterious and simultaneous oxidation of the silicon substrate. After a layer of 1-3 monolayers of the monocrystalline oxide is grown, the growth is stopped and the crystal quality of that layer is improved by a higher temperature anneal. Following the anneal, the thickness of the layer can be increased by restarting the low temperature growth. An amorphous silicon oxide layer can be grown at the interface between the monocrystalline metal oxide layer and the silicon substrate after the thickness of the monocrystalline oxide reaches a few monolayers.

Method for growing a monocrystalline oxide layer and for fabricating a semiconductor device on a monocrystalline substrate

A fuel cell device and method of forming the fuel cell device including a base portion having a major surface. At least one fuel cell membrane electrode assembly is formed on the major surface of the base portion. A water recovery and recirculation system is defined in a cap portion and in communication with a water recovery and recirculation channel defined in the base portion. The water recovery and recirculating system is formed to collect reaction water from the cathode side of the at least one fuel cell membrane electrode assembly for recirculation to the anode side of the fuel cell membrane electrode assembly. An exhaust separation chamber is defined in the base portion and communicating with the fuel cell membrane electrode assembly for the exhausting of generated gases.

Direct methanol fuel cell including a water recovery and re-circulation system and method of fabrication

A thermoelectric material is disclosed that is manufactured from a method including the steps of: providing a Group IV element boride, and doping the Group IV element boride with a doping element chosen from one of the column III, IV, V elements, wherein the doping element is different from the Group IV element in the Group IV element boride, and the doping element is not boron. An alternate method of fabricating a thermoelectric material includes the steps of simultaneously growing on a substrate a Group IV element boride and at least one doping element chosen from one of the Group III, IV, or V elements wherein the doping element is different than the Group IV element in the Group IV element boride and the doping element is not boron.

High performance thermoelectric material and method of fabrication

A method of fabricating a field effect transistor including doping a continuous blanket layer in a semiconductor substrate structure adjacent the surface to include a source area and a drain area spaced from the source area. A high dielectric constant insulator layer is positioned on the surface of the semiconductor substrate structure overlying the continuous blanket layer to define a gate area between the source and drain areas. A gate contact on the insulator layer is selected to provide a work function difference that depletes the doped layer beneath the insulator layer. Further, the doped layer depth and dosage are designed such that the doped layer is depleted beneath the insulator layer by the selected work function difference of the gate contact and the semiconductor substrate.

Method and apparatus for creating a voltage threshold in a FET

A thermoelectric power generator and method of generating thermoelectric power in a steam power cycle utilizing latent steam heat including a condenser, a heat source, such as steam, and at least one thermoelectric module. The condenser includes a plurality of condenser tubes each having included therein a heat extractor. The heat source is in communication with the condenser and is characterized as providing thermal energy to the condenser. The at least one thermoelectric module, including a plurality of thermoelectric elements, is positioned in communication with at least one of the plurality of condenser tubes so that thermal energy flows through the thermoelectric elements thereby generating electrical power.

Thermoelectric power generator and method of generating thermoelectric power in a steam power cycle utilizing latent steam heat

A method of etching a layer of electrical insulating material including a layer of strontium titanate on a surface of a semiconductor substrate. The layer of strontium titanate is immersed in a passivated etching solution including an acid and HF and focused light is directed onto the surface of the layer of strontium titanate at areas to be etched, so as to depassivate the passivated surface and to etch the layer of strontium titanate only at the surface receiving collimated light. In a preferred embodiment, the passivated etching solution includes HCl and less than 1000 ppm of HF.

Technique for etching oxides and/or insulators

A field effect transistor with an enhanced dielectric constant gate insulator including spaced apart source and drain terminals positioned on a substrate structure so as to define a gate area therebetween. A layer of laterally strained, enhanced dielectric constant dielectric material is epitaxially grown on the substrate structure in the gate area, and a gate metal is positioned on the layer of dielectric material to form a gate terminal in the gate area.

Enhanced dielectric constant gate insulator

A ferroelectric semiconductor device (10) and a method of manufacturing the ferroelectric semiconductor device (10). The ferroelectric semiconductor device (10) is manufactured from a substrate (11) that has a layer (14) of ferroelectric material sandwiched between a substrate (13) and a layer (16) of silicon. A gate structure (24) is formed on the layer (16) of silicon. A source region is formed in a portion of the layer (16) of silicon adjacent one side of the gate structure (24) and a drain region is formed in a portion of the layer (16) of silicon adjacent an opposing side of the gate structure (24).

Ferroelectric semiconductor device, and ferroelectric semiconductor

Quantum random address memory apparatus including a low dimensional plurality of address ports, a plurality of nano-memory elements, nano-diodes coupling the address ports to a high dimensional plurality of the plurality of nano-memory elements, and data output ports and structure coupled to the plurality of nano-memory elements. The high dimensional plurality of nano-memory elements is greater than the low dimensional plurality of address ports by a number resulting in substantially error free memory recalls.

Growing community of inventors

Chandler, AZ, United States of America

Daniel S Marshall