Intel Corporation

Daniel S Klowden

Adarsh Panikkar

S Reji Kumar

Abhimanyu Kolla

Vivek K De

Siva G Narendra

James W Tschanz

Dheeraj R Subbareddy

Ankireddy Nalamalpu

Md Altaf Hossain

Joshua B Fryman

Sandeep B Sane

Mahesh K Kumashikar

Nitin Y Borkar

Anshuman Thakur

Jason M Howard

Kersi H Vakil

Robert Pawlowski

Kemal Aygün

Bharadwaj Krishnamurthy

Byoungchan Oh

Shruti Sharma

Jing Fang

Casey Thielen

Systems, methods, and apparatuses for direct memory access instruction set architecture support for flexible dense compute using a reconfigurable spatial array are described. In one embodiment, a processor includes a first type of hardware processor core that includes a two-dimensional grid of compute circuits, a memory, and a direct memory access circuit coupled to the memory and the two-dimensional grid of compute circuits; and a second different type of hardware processor core that includes a decoder circuit to decode a single instruction into a decoded single instruction, the single instruction including a first field to identify a base address of two-dimensional data in the memory, a second field to identify a number of elements in each one-dimensional array of the two-dimensional data, a third field to identify a number of one-dimensional arrays of the two-dimensional data, a fourth field to identify an operation to be performed by the two-dimensional grid of compute circuits, and a fifth field to indicate the direct memory access circuit is to move the two-dimensional data indicated by the first field, the second field, and the third field into the two-dimensional grid of compute circuits and the two-dimensional grid of compute circuits is to perform the operation on the two-dimensional data according to the fourth field, and an execution circuit to execute the decoded single instruction according to the fields.

Circuitry and methods for direct memory access instruction set architecture support for flexible dense compute using a reconfigurable spatial array

Embodiments herein relate to systems, apparatuses, or processes for improving off-package edge bandwidth by overlapping electrical and optical serialization/deserialization (SERDES) interfaces on an edge of the package. In other implementations, off-package bandwidth for a particular edge of a package may use both an optical fanout and an electrical fanout on the same edge of the package. In embodiments, the optical fanout may use a top surface or side edge of a die and the electrical fanout may use the bottom side edge of the die. Other embodiments may be described and/or claimed.

Electrical and optical interfaces at different heights along an edge of a package to increase bandwidth along the edge

In general, in one aspect, the disclosure describes an apparatus including a first deskew unit and a second deskew unit. The first deskew unit operates at a first clock domain and provides fine timing adjustment to a signal. The second deskew unit operates at a second clock domain that is slower than the first clock domain and provide coarse timing adjustment to the signal.

Dual clock domain deskew circuit

Some embodiments of the invention provide a training sequence that may be used in a deskewing process or a protocol to be implemented in a training sequence deskew. Embodiments may also comprise a training pattern that allows for header or frame alignment.

Training pattern based de-skew mechanism and frame alignment

In some embodiments an apparatus and method may comprise a plurality of lanes between two clock domains, each lane comprising circuitry to generate a first signal when the lane may lose cycle coherency with other of the plurality of lanes, generate a second signal to signify a lane has been delayed, and a control circuit coupled with the plurality of lanes to add latency only to lanes that did not generate a second signal if the control circuit detects a first signal from any of the plurality of lanes.

Delaying lanes in order to align all lanes crossing between two clock domains

An apparatus for and method of modifying an IC design layout of an integrated circuit, comprising: accessing an initial IC design layout, with the initial layout including a plurality of MOSFET devices having a common substrate; and removing a plurality of body contacts of the MOSFET devices to create a first modified IC design layout.

IC design process including automated removal of body contacts from MOSFET devices

Growing community of inventors

Denver, CO, United States of America

Daniel S Klowden