Intel Corporation

Tektronix, Inc.

Daniel S Froelich

Debendra Das Sharma

Sam J Strickling

Michelle L Baldwin

Lin-Yung Chen

David J Harriman

Mahesh U Wagh

James E Jaussi

Jonathan San

Shane A Hazzard

Abdul Rahman Ismail

Sean O Stalley

Venkatraman Iyer

Zuoguo Wu

Fulvio Spagna

Michelle C Jen

Jed H Andrews

Per E Fornberg

Sarah R Boen

David Edward Bradley

Su Wei Lim

Rahul R Shah

Bruce A Tennant

Eric M Lee

Quinn Devine

Andrew Mccann

Akshay Pethe

Systems and methods for automated recognition of a device under test and retrieving data associated with the device under test based on the recognition. The systems and methods include receiving a recognition key based on an identifying characteristic of the device under test, matching the received recognition key to a stored key in a database, retrieving data related to the stored key when the received recognition key matches the stored key, transmitting instructions to perform an action on a test and measurement device based on the retrieved data, receiving new data related to the device under test, and updating the data in the database related to the stored key with the new data.

Automated recognition of a device under test

A calibrated test and measurement cable for connecting one or more devices under test and a test and measurement instrument, including a first port structured to electrically connect to a first signal lane, a second port structured to electrically connect to a second signal lane, a third port structured to electrically connect to a test and measurement instrument, and a multiplexer configured to switch between electrically connecting the first port to the third port and connected the second port to the third port. The first and second signal lanes can be included on the same device under test or different devices under test. An input can receive instructions to operate the multiplexer.

Multiplexer-enabled cables and test fixtures

A test and measurement system has a test and measurement instrument having an adaptor with an interface configured to communicate through one or more communications links with a new device under test to receive new test results, a memory configured to store a database of test results and a database of analyzed test results related to tests performed with one or more prior devices under test, a data analyzer connected to the test and measurement instrument through the one or more communications link, the data analyzer configured to analyze the new test results based on the stored test results, and a health score generator configured to generate a health score for the new device under test based on the analysis from the data analyzer.

Test and measurement system for analyzing devices under test

Aspects of the embodiments are directed to systems, methods, and computer program products that facilitate a downstream port to operate in Separate Reference Clocks with Independent Spread Spectrum Clocking (SSC) (SRIS) mode. The system can determine that the downstream port supports one or more SRIS selection mechanisms; determine a system clock configuration from the downstream port to a corresponding upstream port connected to the downstream port by the PCIe-compliant link; set an SRIS mode in the downstream port; and transmit data across the link from the downstream port using the determined system clock configuration.

System, method, and apparatus for SRIS mode selection for PCIE

Systems, devices and methods for high-speed I/O margin testing can screen high volumes of pre-production and production parts and identify cases where the electrical characteristics have changed enough to impact operation. The margin tester disclosed is lower cost, easier to use and faster than traditional BERT and scopes and can operate on the full multi-lane I/O links in their standard operating states with full loading and cross-talk. The margin tester assesses the electrical receiver margin of an operation multi-lane high speed I/O link of a device under test simultaneously in either or both directions. In a technology-specific form, an embodiment of the margin tester can be implemented as an add-in card margin tester to test motherboard slots of a mother board under test, or as a as a motherboard with slots to test add-in cards.

Systems, methods and devices for high-speed input/output margin testing

A margin tester including an identification reader configured to receive an adaptor identifier of an adaptor, an interface configured to connect to a device under test through the adaptor, and one or more processors configured to assess a margin, such as an electrical margin or an optical margin, of a device under test and tag the assessment with the adaptor identifier. Assessing the margin can include assessing the margin based on an expected margin that is predicted or provided based on the adaptor identifier.

Margin test data tagging and predictive expected margins

A cable structured to be repeatedly connected to a device, each repeated connection causing degradation of the cable, the cable including a condition indicator disposed on the cable and configured to be updated with each successive connection of the cable into the device.

Cable condition indicator

A margin testing device includes at least one interface structured to connect to a device under test (DUT) one or more controllers structured to create a set of test signals based on a sequence of pseudo random data and one or more pre-defined parameters, and an output structured to send the set of test signals to the DUT. Methods and a system for testing a DUT with the disclosed margin tester and other testing device are also described.

Systems, methods, and devices for high-speed input/output margin testing

Systems, devices and methods for high-speed I/O margin testing can screen high volumes of pre-production and production parts and identify cases where the electrical characteristics have changed enough to impact operation. The margin tester disclosed is lower cost, easier to use and faster than traditional BERT and scopes and can operate on the full multi-lane I/O links in their standard operating states with full loading and cross-talk. The margin tester assesses the electrical receiver margin of an operation multi-lane high speed I/O link with a device under test simultaneously in either or both directions. In a technology-specific form, an embodiment of the margin tester can be implemented as an add-in card margin tester to test motherboard slots of a mother board under test, or as a as a motherboard with slots to test add-in cards.

A system for data creation, storage, analysis, and training while margin testing includes a margin test generator coupled through an interface to a Device Under Test (DUT). The margin test generator is structured to modify test signals for testing the DUT during one or more testing states of a test session to create testing results. The testing results are stored in a data repository along with a DUT identifier of the DUT tested during the test session. A comparator determine whether any results of the DUT test results match a predictive outcome that is based from an analysis of previous DUT tests. If so, a message generator produces an indication that the tested DUT matched the predictive outcome.

A test and measurement system for analyzing a device under test, including a database configured to store test results related to tests performed with one or more prior devices under test, a receiver to receive new test results about a new device under test, a data analyzer configured to analyze the new test results based on the stored test results, and a health score generator configured to generate a health score for the new device under test based on the analysis from the data analyzer.

A test mode signal is generated to include a test pattern and an error reporting sequence. The test mode signal is sent on link that includes one or more extension devices and two or more sublinks. The test mode signal is to be sent on a particular one of the sublinks and is to be used by a receiving device to identify errors on the particular sublink. The error reporting sequence is to be encoded with error information to describe error status of sublinks in the plurality of sublinks.

Interconnect retimer enhancements

System, method, and apparatus for SRIS mode selection for PCIe

A port of a computing device includes multiple receiver-transmitter pairs, each of the receiver-transmitter pairs including a respective receiver and a respective transmitter. The device further includes state machine logic that detects a training sequence received by a particular one of the receiver-transmitter pairs on a particular lane from a tester device. The training sequence includes a value to indicate a test of the particular receiver-transmitter pair by the tester device. The particular receiver-transmitter pair enters a first link state in association with the test and one or more other receiver-transmitter pairs of the port enter a second link state different from the first link state in association with the test to cause crosstalk to be generated on the particular lane during the test.

Growing community of inventors

Portland, OR, United States of America

Daniel S Froelich