International Business Machines Corporation

Daniel Rodko

Pradip Patel

William Vincent Huott

Yuen H Chan

Harry S Barowski

Sheldon Bernard Levenstein

Rolf Sautter

Gordon B Sapp

Otto Andreas Torreiter

Thomas J Knips

Thomas Gentner

Uma Srinivasan

Hagen Schmidt

Matthew Steven Hyde

Kirk David Peterson

Franco Motika

Norman Karl James

John B DeForge

Timothy Meehan

Hyong Uk Kim

Michelle E Finnefrock

Kevin J Duffy

A method for testing a circuit includes performing, by a test engine, a test of bit write to a memory. The test includes defining a bit group based on a set of bits from an address of a memory location. The test further includes generating a bit mask for the bit group. The test further includes performing a bit write operation to the address to store a sequence of bits, the sequence of bits selected using a predetermined bit pattern. The test further includes reading content of the address. The test also includes comparing, using the bit mask, only bits corresponding to the bit group from the sequence of bits and from the content of the address.

Testing bit write operation to a memory array in integrated circuits

A system may include an integrated circuit having repair select bits coupled with a central repair register. The repair register may be configured to determine how to broadcast multiple repair actions to a group of repairable circuits. Inclusion of the repair register may function to reduce the total number of latches used to hold repair information.

Microchip level shared array repair

A non-limiting example includes data storage circuitry. The data storage circuitry includes a built-in self-test (BIST) engine. The data storage circuitry includes a memory array including memory cells. The memory array is configured to store data based on a read-write vector associated with an address vector that includes memory addresses and according to a bit-write vector that defines bit-write enablement for the memory addresses. The memory array is configured to output a stored data vector. The data storage circuitry includes a selector configured to receive the bit-write vector, and to output a selected vector based on an initialization vector and a comparison vector based at least in part on the bit-write vector. The data storage circuitry includes a comparator configured to receive the stored data vector and the selected vector, and to output an error based on discrepancies between the stored data vector and the selected vector.

Built-in self-test for bit-write enabled memory arrays

Embodiments of the present invention are directed to methods, systems, and circuitry for memory arrays. A system for testing a memory array having self-test circuitry includes a register having register latches operable to receive error logic signals having respective first states or second states. The register latches are arranged in series having respective latch inputs cascaded with preceding latch outputs operable to shift the error logic signals to a serial output according to a control signal that is common to the register latches. The system includes an aggregate latch operable to receive the serial output and having input logic configured to maintain a first state of the aggregate latch until the serial output is a second state. The system includes a built-in self-test (BIST) engine including stored instructions operable upon execution by the BIST engine to output the control signal.

Sequential error capture during memory test

Techniques for a power saving scannable latch output driver in an integrated circuit (IC) are described herein. An aspect includes receiving, by a circuit comprising a scannable latch, a scan signal. Another aspect includes, based on the scan signal being enabled, turning on a scan output driver of the scannable latch, wherein a scan input of the scannable latch propagates through the scannable latch to a scan output based on the scan output driver being turned on. Another aspect includes, based on the scan signal being disabled, turning off the scan output driver, wherein the scan output driver comprises a first p-type field effect transistor (PFET) and a first n-type field effect transistor (NFET), wherein a gate of the first PFET and a gate of the first NFET are connected to an output of a latch of the scannable latch.

Power saving scannable latch output driver

The present invention provides a system and method of testing CAMs and RAMs. In an exemplary embodiment, the system includes a multiple input signature register (MISR) logically coupled to digital outputs of a CAM, to digital inputs of a RAM, and to digital outputs of an ABIST controller circuit, where the MISR includes a plurality of L1 latch circuits logically coupled to a plurality of L2 latch circuits, a plurality of multiplexer circuits logically coupled to the plurality of L1 latch circuits, a plurality of exclusive or circuits (inner XOR circuits) logically coupled to the plurality of MUX circuits and to the plurality of L2 latch circuits, and at least two XOR circuits (outer XOR circuits), each of the outer XOR circuits logically coupled to one of the inner XOR circuits, to at least one of the MUX circuits, and to at least one of the L2 latch circuits.

Testing content addressable memory and random access memory

An integrated circuit with a hardware-based controller enables a system for a set of clock cycles and selectively enables an aspect of the system for a subset of the set of clock cycles. The controller includes a clock cycle select circuit to output a test select signal that indicates the subset of the set of clock cycles during which to enable the aspect of the system, and a test start circuit to receive the test select signal and output a test signal to the system to enable the system for the set of clock cycles. The controller also includes an AND gate to output a gated signal to enable the aspect of the system for the subset of the set of clock cycles based on the test select signal.

On-chip hardware-controlled window strobing

Aspects of present disclosure relate to an integrated circuit chip (chip), a method and a computer program product of testing the chip. The method of testing the chip may include: partitioning the chip into various partitions, loading built-in self-test (BIST) test instructions into BIST engine and initializing a current partition counter, performing BIST test on current partition, transmitting test results of the current partition of the chip to an external test data storage, checking whether current partition is the last partition, incrementing current partition counter, and returning to performing BIST on a next partition when current partition is not the last partition, and exiting BIST test when current partition is the last partition. The test results may be stored in one or more inactive storage elements of the chip. The number of partitions may include: one partition, a predetermined number of partitions, and a variable number of partitions.

Partition-able storage of test results using inactive storage elements

An aspect includes a method of multi-match error detection in content addressable memory (CAM) testing. The method includes loading a content addressing row of a CAM section with a row test address word. Data value rows of a random access memory (RAM) section are loaded with unique test patterns in each of the data value rows having a same number of on-state bits per data value row. A row test is initiated to search for a matching content addressing row in the CAM section corresponding to the row test address word. A row test result is received as one or more data value rows from the RAM section identified as having a content addressing row in the CAM section that matches the row test. The row test result is compared to an aspect of one or more of the unique test patterns to determine whether the row test has failed.

Multi-match error detection in content addressable memory testing

Aspects include a computer-implemented method for scanning data into a shift register. The method includes receiving, by a circuit, a data signal, wherein the data signal propagates in a first direction; and receiving, by the circuit, a clock signal, wherein the clock signal propagates in a second direction, wherein the second direction is in a reverse direction of the first direction.

Shift register with opposite shift data and shift clock directions

An array built-in self test (ABIST) system includes a first latch having a first data input, a first scan input and first output and a second latch having a second data input, a second scan input and a second output. The system also includes a first ABIST logic block coupled to the first output that compares a first expected value with a first data value received at the first data input and provided to the first ABIST logic block after a first clock is applied to the first latch. The system also includes a second ABIST logic block coupled to the second output that compares a second expected value with a second data value received at the second data input and provided to the second ABIST logic block after a second clock is applied to the second latch.

Memory testing system

Disclosed is testing multi-port array macros where latches and logic are used to control the relationship between the write and read port of the array. This makes allowance for many different configurations of reading and writing the array. This also allows for greater test coverage than the previous method, which simply inverted one of the write address bits to form the read address.

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Poughkeepsie, NY, United States of America

Daniel Rodko