International Business Machines Corporation

Daniel Richard Menard

Mark R Lasher

Keith M Carrig

Phillip Paul Normand

Thomas Walker Fry

Joseph N Kozhaya

Paul Gerard Villarrubia

Christopher J Berry

Michael H Wood

Roger Paul Gregor

Janice M Adams

Phillip P Normand, Ii

Amanda Christine Venton

Philip P Normand

Geetha Arthanari

Susan R Sanicky

Embodiments of the disclosure relate to methods for facilitating the design of a clock grid in an integrated circuit. The method includes propagating a chip level virtual grid across a multi-level hierarchy of the integrated circuit and customizing the grid at each macro to create a customized virtual grid for each macro. The method further includes propagating the customized virtual grid for each of the plurality of macros to one of a plurality of units and customizing the chip level virtual grid at each of the plurality of units to create the customized virtual grid for each of the plurality of units. The method also includes propagating the customized virtual grid for each of the plurality of units to the chip level and combining the plurality of customized virtual grids to form the clock grid for the integrated circuit.

Facilitating the design of a clock grid in an integrated circuit

A method, system and computer program product for implementing enhanced clock tree distributions to decouple across N-level hierarchical entities of an integrated circuit chip. Local clock tree distributions are constructed. Top clock tree distributions are constructed. Then constructing and routing a top clock tree is provided. The local clock tree distributions and the top clock tree distributions are independently constructed, each using an equivalent local clock distribution of high performance buffers to balance the clock block regions.

Implementing enhanced clock tree distributions to decouple across N-level hierarchical entities

A method of designing a clock tree in an integrated circuit combines steps of making a list of all clock sinks; positioning a temporary reference insertion point (TIP); grouping the sinks together with structured clock buffers (SCBs) in a set of levels; and moving the SCBs to improve symmetry of the tree. The SCBs may be of several sizes and may be positioned horizontally or vertically and moved within limits to permit the program to calculate a complete tree.

ASIC clock floor planning method and structure

A method for signal balancing across multiple random logic macros. The method inserts a programmable delay element into the design before the last buffer level on all signal paths. The random logic macro is then fully designed including cell placement and wiring. With programmable delay buffers in place, the random logic macros may be used within multiple designs, each having varying signal latency requirements.

Programmable delay method for hierarchical signal balancing

A method for balancing signals across an IC design having multiple voltage domains. The method uses a voltage tress to balance the signals at the top level above the voltage domains. Then using worst case and best case signal latencies determines the average latency in each voltage domain. Then balancing signals at the other levels of the design by incrementing the latencies in each domain until a target level based on the slowest average latency is reached.

Signal balancing between voltage domains

An integrated circuit chip comprises a plurality of clock distribution sub-networks each including a clock input for receiving a clock signal, each of the clock distribution sub-networks having a capacitance, as seen from the clock input, substantially equivalent to others of the clock distribution sub-networks; and a structured clock buffer having a size based on a load of the clock distribution sub-networks, and providing the clock signal to the clock distribution sub-networks.

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Daniel Richard Menard