International Business Machines Corporation

Daniel Ray Knebel

Jeffrey Alan Kash

James C Tsang

Stephen Victor Kosonocky

Pia Naoko Sanda

Suhwan Kim

James Chen-Hsiang Tsang

Li-Kong Wang

William Robert Reohr

Stanislav Polonsky

Phillip J Nigh

Richard James Evans

Steven H Voldman

Mark Alan Lavin

Azeez Jennudin Bhavnagarwala

David P Vallett

Sam Gat-Shang Chu

Leendert M Huisman

Subhrajit Bhattacharya

David F Heidel

Harold Wayne Chase

Stephen J Barnfield

Jamie H Moreno

Xiaodong Xiao

Dennis G Menzer

A number of performance parameters for the electronic system are determined at a particular age of the electronic system. The performance parameters can be correlated to maximum operating frequency of electronic components of the electronic system for the particular age of the electronic system. Operating frequency of the electronic components is adjusted in accordance with the performance parameters. The performance parameters may be predetermined (such as through reliability and burn-in testing), determined during the life of the electronic system, or some combination of these. Performance parameters can comprise prior operating frequencies, hours of operation, ambient temperature, and supply voltage. Performance parameters can comprise performance statistics determined using age-monitoring circuits, where an aged circuit is compared with a circuit enabled only for comparison. Performance statistics may also be determined though error detection circuits. If an error is detected, the operating frequency can be reduced.

Frequency modification techniques that adjust an operating frequency to compensate for aging electronic components

An integrated circuit and method are provided for preventing reverse engineering by monitoring light emissions emitted from transistors and such electrically active devices in the integrated circuit. The method prevents, in an integrated circuit, a pattern of light emitted from at least one active device in the integrated circuit from being detected external to the integrated circuit by fading the light emitted from the at least one active device in the integrated circuit and that is emitted external to the integrated circuit. Bright light emission emitted in substantial close proximity to the at least one active device in the integrated circuit, and emitted external to the integrated circuit, fades a pattern of light emission emitted from the at least one active device.

Device for defeating reverse engineering of integrated circuits by optical means

An integrated circuit and method are provided for preventing reverse engineering by monitoring light emissions emitted from transistors and such electrically active devices in the integrated circuit. The method prevents, in an integrated circuit, a pattern of light emitted from at least one active device in the integrated circuit from being detected external to the integrated circuit by reduction of the intensity of light emitted from the at least one active device in the integrated circuit thereby preventing the reduced intensity light emitted from the at least one active device in the integrated circuit from being detected external to the integrated circuit. The intensity of light emitted from the at least one active device in the integrated circuit can be reduced by modification of operational characteristics of the at least one active device during switching transitions.

An integrated circuit and method are provided for preventing reverse engineering by monitoring light emissions emitted from transistors and such electrically active devices in the integrated circuit. The method prevents, in an integrated circuit, a pattern of light emitted from at least one active device in the integrated circuit from being detected external to the integrated circuit by randomizing a pattern of light emitted from the at least one active device in an integrated circuit and that is emitted external to the integrated circuit. The pattern of light emitted from the at least one active device in the integrated circuit and that is emitted external to the integrated circuit can be randomized by randomizing a clock signal applied to a clocked circuit comprising the at least one active device in the integrated circuit.

A method for an electronic device is provided for preventing reverse engineering by monitoring light emissions emitted from transistors and such electrically active devices in the electronic device. The method emits extraneous randomized light emissions in substantial close proximity to the transistors to hide a pattern of light emissions emitted from the transistors. As one feature, the device can include a source of randomized light emissions in substantial close proximity to the transistors to hide a pattern of the emitted light from the transistors in randomized light emissions emitted by the source. As a second feature, the device can emit the randomized light emissions by randomly delaying an electrical signal that is electrically coupled to the transistors and, in response to the randomly delayed electrical signal, the transistors randomly emitting light emissions thereby hiding a separate pattern of light emission emitted from the transistors.

Method for defeating reverse engineering of integrated circuits by optical means

Techniques are provided for a register file cell that includes a primary storage portion configured to store a first value, and a secondary storage portion that is coupled to the primary storage portion. The secondary storage portion is configured to function as a scan latch during a test operation, and is further configured to store a second value during normal operation. The second value is a duplicate of the first value. The cell further includes an error detection portion that is coupled to the primary storage portion and the secondary storage portion and is configured to indicate a difference between the first value and the second value, caused by a soft error.

Register file cell with soft error detection and circuits and methods using the cell

A method, system and computer program product for modeling and simulating a powergated hierarchical element of an integrated circuit is disclosed. In modeling a powergated macro, the invention does not model all logic gates or elements as powergated, instead, the invention only models latches as connected to an integrated switch to be powergated. In addition, a fence circuit attached to the powergated macro is modeled as including an extra control signal to force a powergated state of the powergated macro into the fence circuit.

Modeling and simulating a powergated hierarchical element

A charge recycling power gate and corresponding method are provided for using a charge sharing effect between a capacitive load of a functional unit and a parasitic capacitance of a charge recycling means to turn on a switching means between a virtual ground and a ground, the charge recycling power gate including a first transistor, a virtual ground in signal communication with a first terminal of the first transistor, a ground in signal communication with a second terminal of the first transistor, a capacitor having a first terminal in signal communication with a third terminal of the first transistor and a second terminal in signal communication with the ground, and a second transistor having a first terminal in signal communication with the virtual ground and a second terminal in signal communication with the third terminal of the first transistor.

Charge recycling power gate

An integrated circuit chip (IC) is equipped with a device for preventing reverse engineering by monitoring light emissions emitted from transistors and such electrically active devices in a circuit located in the IC. The device emits extraneous randomized light emissions in substantial close proximity to the transistors to hide a pattern of light emissions emitted from the transistors. As one feature, the device can include a source of randomized light emissions in substantial close proximity to the transistors to hide a pattern of the emitted light from the transistors in randomized light emissions emitted by the source. As a second feature, the device can emit the randomized light emissions by randomly delaying an electrical signal that is electrically coupled to the transistors and, in response to the randomly delayed electrical signal, the transistors randomly emitting light emissions thereby hiding a separate pattern of light emission emitted from the transistors.

An integrated circuit chip (IC) is equipped with a device for preventing reverse engineering by monitoring light emissions emitted from transistors and such electrically active devices in a circuit located in the IC. The device can be an opaque structure that blocks emissions from being detected external to the IC. Alternatively, the device can reduce light emissions from the transistors to prevent detection of the light emissions external to the IC. The device, in another alternative, can emit extraneous light emissions to hide a pattern of light emissions emitted from the transistors. As a further alternative, the device can add random delay to a signal driving the transistors to randomize the pattern of light emissions emitted from the transistors to prevent detection of a predetermined pattern of light emissions external to the IC.

A method for characterizing circuit activity in an IC. Generally, the method comprises the steps of activating an IC, resolving the switching activity in space and time, and generating a representation of the switching behavior which differentiates the time that circuits or transistors switch. One embodiment of the invention, utilizes a method such as, but not limited to, time resolved photon emission to observe transistor level switching activity in an integrated circuit (IC).

Method for VLSI system debug and timing analysis

A power gate structure and corresponding method are provided for controlling the ground connection of a logic circuit for a plurality of modes, where the power gate structure includes an NFET transistor, a PFET transistor in signal communication with the NFET transistor, source to source and drain to drain, respectively, a ground node in signal communication with the drains of the transistors, and a ground rail in signal communication with the sources of the transistors; and the corresponding method includes decoupling the logic circuit from the ground connection in a first or active mode, holding the logic circuit at about a threshold voltage above the ground connection in a second or state retention mode, and cutting off the current flow between the logic circuit and the ground connection in a third or non-state retentive mode.

Digital logic with reduced leakage

A method and system for visualizing circuit operation. In the method device activity is obtained based on one or more of measured or simulated activity. The device activity is expressed in a representation, and the expressed activity is represented in a visual form. One suitable form of activity is the simulated version of the PICA slow motion movie. The invention may apply to other simulated design data vies as well, such as switch level simulation, current density simulation, and power density simulation.

Growing community of inventors

Carmel, NY, United States of America

Daniel Ray Knebel