Compagnie Internationale Pour L'informatique Cii-honeywell Bull (societe

Compagnie Internationale Pour L'informatique Cii-honeywell Bull

Daniel R Vinot

Jacques Michel Bienvenu

Robert J Bavoux

Pierre Gabriel Antoine

A control logic circuit (C) is provided in each unit such as processors and emories in a multiple processor data processing system. Each control logic circuit (C) is equipped with a priority circuit (P12) which at one input receives the eligible local calls (RQ.sub.i L) of the unit itself and at the other input receives external calls (RQ.sub.k) transmitted by the other units. The control logic circuit (C) enables control by its unit of a transmission but only when its priority circuit (P12) recognizes that unit as having the highest priority among the other units. The logic circuit (C) together with a T circuit (13) selects local calls as a function of the state of occupation of the data lines of the transmission bus.

Device for superimposition of the successive stages of the transfer of

A central sub-system of a data processing system, including an operator console controlling a service processor, is divided into several sub-units, functioning separately from each other. The sub-units include processors that are connected together and to a common controller for a common memory unit by data, address and control buses. Each sub-unit includes a configuration device that stores an appurtenance indicator derived from the service processor in response to sub-unit initialization, and enables its associated sub-unit to exchange data with the memory unit. The sub-unit having the highest priority of the sub-units attempting to access the memory units is connected to the memory unit by the controller. A single configuration memory stores an indication of the sub-units in service in the central sub-system. The configuration memory is addressed each time the memory unit is addressed by a signal indicative of the appurtenance indicator derived from the selected sub-unit. The configuration memory derives an authorization signal that commands performance of memory cycles by the selected unit when the configuration memory contains an indication that the selected sub-unit is in service in the sub-system. The controller includes memorization means for storing the highest priority sub-unit trying to access the memory unit. The memorization means derives an output that is coupled to the data address and control buses to transmit a signal indicative of the number of the sub-unit with data to be exchanged with the memory unit to each of the authorizing means, thereby to establish data transmission between the sub-unit having the highest priority and the memory unit.

Device wherein a central sub-system of a data processing system is

An apparatus for transferring data blocks of variable lengths between intaces of different widths. The apparatus includes a series memory of the first-in, first-out type (FIFO) and an interface means at the input and output of the series memory. The interface means has a first means for storage of input data words and a second means for storage of output data words, the two storage means being of different storage capacity. Means are included for signalling to external devices when the first storage means and the series memory are empty and ready to receive data. Means are also included for controlling in response to an external signal the width of the output data words.

Apparatus enabling the transfer of data blocks of variable lengths

A method for storing a binary signal in a high speed flip-flop memory. The apparatus includes a clock signal selecting device connected to control a pair of memory elements in cascade. Data is introduced into the first memory element under the control of a first control signal from the clock signal selecting device and is transferred to the second memory element under the control of a second control signal from the clock signal selecting device. A single output of a clock pulse generator is applied via parallel lines, one of which includes a delay element, to a logic gate to provide spaced time pulses which are applied to the clock signal selecting device. The clock signal selecting device includes a pair of two input AND gates, each of which are connected to receive at one input the spaced time pulses and at the second input a clock signal selecting signal derived from the output of a JK flip-flop having its sync input connected to receive the spaced time pulses.

Method for storing a binary signal in a high speed flip flop memory

A high capacity associative read/write memory is provided which includes storage means which can be read from or written into and having memory units of equal capacity each containing an equal and predetermined number of levels. Addressing means are coupled to the memory for addressing the data locations in the memory. A first comparator compares the content of the memory addressed (the data descriptor word) with the words read from the associative memory and a second comparator compares the content of the words read from the associative memory with the content of a descriptor containing the memory word to be invalidated. The number of comparators is equal to twice the number of memory levels multiplied by the number of memory units and is independent of the capacity of the memory. The outputs of the comparators are multiplexed to enable it to be used in the normal mode or in an associative mode.

Associative memory

A high capacity associative read/write memory is provided which includes storage means which can be read from or written into and having memory units of equal capacity each containing an equal and predetermined number of levels. Addressing means are connected to the storage means to select storage levels in each memory unit and to select the required memory location on the selected level. Associative means connected to the storage means consists of a plurality of comparators equal in number to the number of levels in each memory unit multiplied by the number of memory units. The comparators perform a comparison between the content of a data descriptor at the input to the associative memory and the content of the information read from the memory on the selected level.

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Sucy en Brie, France

Daniel R Vinot