Apple Inc.

Integrated Device Technology, Inc.

Google Inc.

Daniel R Steinberg

Cesar A Talledo

Hui Zhang

Alexander B Beaman

Qi Bian

According to one general aspect, a method may include simulating a memory circuit, wherein the memory circuit is configured to store data. The method may also include receiving, by the simulated memory circuit, a memory access operation. The method may further include dynamically determining, in response to the memory access, if, based on a set of predefined criteria, the simulated memory circuit should generate a memory error as the result of the memory access. The method may also include, if the simulated memory circuit is to generate the memory error, generating the memory error as the result of the memory access.

Constrained random error injection for functional verification

A content-based comparison of a plurality of digital audio signals can be performed by generating, for a portion of a corresponding channel, a first set of spectral characteristics associated with a first audio signal and a second set of spectral characteristics associated with a second audio signal; comparing the first set of spectral characteristics with the second set of spectral characteristics to identify a degree of difference; and determining, for the portion of the corresponding channel, whether the first audio signal is substantially identical to the second audio signal based on the identified degree of difference. Further, one or more match criteria can be received from a user and utilized to determine, for the portion of the corresponding channel, that the first audio signal is substantially identical to the second audio signal if the identified degree of difference is within the received match criteria.

Content-based audio comparisons

A reader and writer access a ring buffer without using a locking mechanism, thereby avoiding any delays attendant to using a locking mechanism when performing read operations to supply the reader with data from the ring buffer. Other measures are used to reduce delayed performance of read operations. If data requested by a reader is not available in the ring buffer, rather than waiting until the data becomes available, substitute data not from the ring buffer is provided instead. The ring buffer's size may be dynamically increased or decreased to improve performance of read and write operations and/or to conserve computer resources.

Lockless access to a ring buffer

A digital audio signal can be processed to have a constant pitch for a range of playback rates. A playback rate associated with a portion of the digital audio signal can be received, which differs from the rate at which the digital audio signal was recorded. A channel of the digital audio signal can be divided into a plurality of windows and one or more cross-correlation evaluations can be performed for at least a first window and a second window of the channel to determine an appropriate overlap. Further, the first cross-correlation evaluation can be performed using an ideal overlap. One or more sample values associated with a first waveform included in the first window can be averaged with one or more corresponding sample values associated with a second waveform included in the second window for the determined appropriate overlap to generate a rate-modified audio signal, which can be played.

Constant pitch variable speed audio decoding

A buffer bypass circuit for reducing latency in information transfers to a bus is described. Access to the bus is governed by a bus arbiter employing a bus parking scheme. The buffer bypass circuit comprises a multiplexer and logic configured such that the information to be transferred is either buffered in a buffer if a grant generated by the bus arbiter indicates that the bus is unavailable, or transferred directly to the bus if the grant indicates that the bus is available and the buffer is empty at the time.

Buffer bypass circuit for reducing latency in information transfers to a bus

Clock processing logic and method for determining clock signal characteristics in reference voltage and temperature varying environments are described. A sample vector is characterized by bit locations corresponding to sequentially increasing delay values so that values stored in such bit locations indicate clock signal edges where value transitions occur. In one embodiment, edge detection logic and sensitivity adjustment logic are used in determining the clock period from such a sample vector. In another embodiment, an edge filter, sample accumulation logic, and clock period and jitter processing logic are used in determining an average clock period and clock jitter from a predefined number of such sample vectors.

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Mountain View, CA, United States of America

Daniel R Steinberg