National Semiconductor Corporation

Microchip Technology Inc.

Daniel R Meacham

Andrea Panigada

Jorge Grilo

Lawrence Jarrett Malone

William J Huff

Ibrahim Yayla

David Shih

Michael Harris

A curvature compensated bandgap circuit that is capable of matching best-in-class two (2) parts-per-million performance without over-temperature trimming. This improves performance metrics for precision voltage reference products without requiring individual device tuning during production thereof. A core bandgap circuit comprises a main operational amplifier having a second order bowed voltage response over temperature. A ptat circuit is coupled to the core bandgap circuit to provide a sigmoidal third order shape for the bandgap voltage.

Simplified curvature compensated bandgap using only ratioed components

An analog input stage has m differential input channels, wherein m&#x3e;1. The analog input stage is configured to select one of the m differential input channels and provide an output signal. The analog input stage has n identical selection units each having m differential channel inputs and one differential output, wherein n is at least 2. Each selection unit is operable to be coupled to any of the differential input channels through respective differential multiplexer units, wherein the multiplexor units are driven to select one of the differential input channels and couple the selected differential channel input through a butterfly switch unit with the differential output of the selection unit. The differential output signals of the n selection units are combined whereby unwanted crosstalk from channels other than a selected channel are removed by cancellation.

Sampling input stage with multiple channels

A circuit in an analog-to-digital converter (ADC) includes an amplifier configured to receive an output of a backend DAC; a harmonic distortion correction circuit (HDC) coupled to the amplifier and configured to correct distortion components due to the residue amplifier present in a digital signal from the backend ADC, the HDC circuit providing an output to an adder, the adder receiving a coarse digital output from a coarse ADC; and a DAC noise cancellation circuit (DNC) configured to provide an output to the adder, wherein the DNC circuit is configured to correct distortion components due to the DAC present in the digital signal from the backend ADC; wherein the output of the adder is an ADC digital output and wherein the ADC digital output forms an input to the HDC and the DNC.

Modified dynamic element matching for reduced latency in a pipeline analog to digital converter

An input circuit for an analog-to-digital converter (ADC) includes at least one bootstrap circuit, including at least one first switch for connecting electrical power to a first terminal of at least one capacitor; at least one second switch for connecting a second terminal of the at least one capacitor to a signal to be sampled; at least one third switch for connecting the first terminal of the at least one capacitor to the control gate of at least one sampling network input switch; at least one fourth switch for connecting the at least one sampling network input switch to a substrate; and at least one fifth switch for connecting the second terminal of the at least one capacitor to the substrate.

Distributed bootstrap switch

A system including a sample-and-hold circuit for receiving a plurality of analog input signals; an analog-to-digital converter for converting each of the analog inputs to a digital signal; and a processor configured for implementing fractional delay recovery for the analog-to-digital converter. In some embodiments, the fractional delay recovery includes converting each of the plurality of analog input signals to a digital version in the predetermined order; upsampling each digital version in the predetermined order; digitally filtering each upsampled value in the predetermined order; and downsampling each filtered value in the predetermined order.

Multichannel analog to digital converter apparatus and method for using

A pipeline ADC is provided in which a DEM function and summation of sequences occur within a flash ADC. According to various aspects of the present disclosure, embedding the processing functions needed for DAC and amplifier error correction with the circuitry of a coarse ADC and rearranging the digital calibration blocks HDC and DNC ensures accurate estimation of the errors.

Using low impedance switches and coupling to a virtual ground, one or more capacitors are selectively switched into or out of an inductive-capacitive resonant circuit portion of an integrated circuit filter to alter the resonant frequency based on a phase difference between the resonant frequency and a reference frequency. The capacitors are sized for a sequence of total capacitances proceeding by halves or doubles between values corresponding to minimum and maximum desired frequency adjustments, allowing a binary count of pulses representative of the phase difference to address the correct combination of capacitors. An exact or ratioed replica of the inductive-capacitive resonant circuit, controlled by the same capacitance selection signal, may be used as a frequency-selective amplifier load or matching network, or to form a ladder filter.

Method and apparatus for tuning RF integrated LC filters

A method includes identifying a setting for a capacitor bank associated with a voltage-controlled oscillator in a closed-loop phase-locked-loop. The setting represents a combination of one or more capacitors in the capacitor bank. The method also includes estimating a gain introduced by the closed-loop phase-locked-loop when the oscillator operates using the identified setting. The method further includes estimating a response of a loop filter in the phase-locked-loop and identifying one or more coefficients for a digital filter using the identified gain and the identified loop filter response. The digital filter is operable to filter an input signal. In addition, the method includes modulating the filtered input signal using the phase-locked-loop to produce an output signal.

Frequency synthesizer using digital pre-distortion and method

A method for stabilizing the performance variation of a primary radio frequency (RF) device is provided that includes providing a secondary RF device. An output signal is generated with the secondary RF device. The output signal is provided to a feedback circuit. A feedback signal is generated based on the output signal with the feedback circuit. The feedback signal is provided to the secondary RF device. The output signal is generated based on the feedback signal. The feedback signal is provided to the primary RF device.

Method and system for stabilizing the performance variation of a radio frequency device

A frequency discriminator for detecting phase shifts between sequential pulses in a frequency-shift keyed (FSK) signal having a nominal frequency, f. The frequency discriminator comprises: 1) a first current controlled delay line for receiving the FSK signal and delaying the FSK signal by a desired time delay to thereby produce a time-delayed FSK signal; 2) a multiplier for receiving and multiplying the FSK signal and the time-delayed FSK signal to thereby produce an output product signal proportional to a phase shift between said FSK signal and said time-delayed FSK signal; and 3) a delay locked loop comprising a second current controlled delay line substantially similar to the first current controlled delay line. The delay locked loop receives a reference clock signal having a time period equal to the desired time delay and adjusts a control current level in the second current controlled delay line until a delay of the second current controlled delay line matches the time period of the reference clock signal. The control current level is then used to adjust a delay of the first current controlled delay line.

Growing community of inventors

Del Mar, CA, United States of America

Daniel R Meacham