Altera Corporation

Daniel R Mansur

Sean R Atsatt

Ali H Burney

Michael David Hutton

Kent Orthner

James G Schleicher, Ii

Sanjay K Charagulla

An field programmable gate array (FPGA) includes a circuit implemented using the FPGA fabric. The FPGA further includes another circuit implemented as hardened circuitry. The FPGA also includes a configurable interface circuit that is adapted to couple together the two circuits.

Apparatus for configurable interface and associated methods

A field programmable gate array ('FPGA') is provided having integrated application specific integrated circuit ('ASIC') fabric. The ASIC fabric may be used to implement one or more custom or semi-custom hard blocks within the FPGA. The ASIC fabric can be made up of a &#x201c;custom region&#x201d; and an &#x201c;interface region.&#x201d; The custom region can implement the custom or semi-custom ASIC design and the interface region can integrate and connect the custom region to the rest of the FPGA circuitry. The custom region may be based on a structured ASIC design. The interface region may allow the ASIC fabric to be incorporated within the hierarchical organization of the FPGA, allowing the custom region to connect to the FPGA circuitry in a seamless manner.

Field programmable gate array with integrated application specific integrated circuit fabric

Various novel aspects are disclosed by reference to an integrated circuit block that includes programmable regions, and extra-block connection pins or points with adapter circuitry, coupled by an interconnect system. Multiple independent interconnects are disclosed within the interconnect system, as are options for the composition of the programmable regions and their connectivity with the interconnect system. Adapter circuitry is disclosed that includes support for coupling extra-block memory circuits or devices using a variety of modes, protocols, and options. Modular circuit blocks provide flexibility at the interface between programmable region and fixed function circuitry.

System and apparatus with IC resource interconnect

Circuitry and methods are provided for control and configuration of a PLD. An embodiment of the invention comprises hard IP circuitry embedded in the PLD. The circuitry may include a gigabit MAC, a hard processor, and a DMA engine. The invention permits a variety of operations, including real-time control and remote programming, without the use of dedicated external circuitry.

Methods and apparatus for control and configuration of programmable logic devices

Methods and apparatus for control and configuration of programmable logic device

Methods and apparatus provide PCI Express support on a programmable device. A device includes a hard-coded transceiver that supports functionality associated with the PCI Express physical layer and link layer. The hard-coded transceiver can also support part of the PCI Express transaction layer. Soft-coded logic is used to support higher layer functionality including a portion of the transaction layer to allow custom configuration of PCI Express features such as virtual channels, buffers, prioritization, and quality of service characteristics. The hybrid solution reduces logic resource cost and provides an effective custom configurable solution.

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Emerald Hills, CA, United States of America

Daniel R Mansur