Intel Corporation

Micron Technology Incorporated

Other

Daniel R Elmhurst

Violante Moschiano

Paul D Ruby

Giovanni Santin

Robert Melcher

Karthikeyan Ramamurthi

Quan H Ngo

Sebastian T Uribe

Fabrice Paillet

June Lee

Kerry Dean Tedrow

Michele Incarnati

Raymond W Zeng

Binh N Ngo

Peter Harrington

Rupinder K Bains

Azam Barkatullah

Ercole Diiorio

Nick Triantafillou

Methods and apparatus for compensating for charge loss in memories include tracking a specific block of the main memory array and determining charge loss compensation by comparing pre-cycled and post-cycled mean threshold voltages for the tracking block; or tracking each block of the main memory and determining charge loss and compensation on a block by block basis.

Charge loss compensation methods and apparatus

In a method of operation, a flash memory cell coupled to a bit-line is programmed, a word-line voltage is coupled to the flash memory cell, a first voltage pulse is coupled to a bias transistor coupled between the bit-line and a sense capacitance at a first time to couple the bit-line to the sense capacitance to generate data to indicate the state of the flash memory cell, a second voltage pulse is coupled to the bias transistor at a second time having a second magnitude that is different from a first magnitude of the first voltage pulse, and a third voltage pulse is coupled to the bias transistor at a third time having a third magnitude that is different from the second magnitude of the second voltage pulse. In a method of operation, the second voltage pulse occurs a first delay period after the first voltage pulse and the third voltage pulse occurs a second delay period after the second voltage pulse, the second delay period being different from the first delay period.

Flash memory and associated methods

In programming a selected word line of memory cells, a first program verify or read operation is performed, after one page of a selected word line is programmed, in order to determine a first quantity of memory cells that have been programmed to a predetermined reference point in the programmed first page distribution. Prior to programming the second page of the selected word line, a second program verify or read operation is performed to determine a second quantity of cells that are still at the reference point. The difference between the first and second quantities is an indication of the quantity of cells that experienced quick charge loss. The difference is used to determine an adjustment voltage for the second page verification operation after programming of the second page.

Charge loss compensation during programming of a memory device

Some embodiments include a die having an output control circuit to interact with an output circuit to convert a source voltage into at least one output voltage. The die may also have a converter circuit to convert the output voltage into at least one additional output voltage.

Multiple output voltage regulator

A flash memory device, such as a NAND flash, is described having an array of floating gate transistor memory cells with strings of memory cells connected to respective bitlines. Structures and methods for selectively pre-charging bitlines are described.

Selective bit line precharging in non volatile memory

Methods and apparatuses for refreshing non-volatile memories due to changes in memory cell charges, such as charge loss, are disclosed. Embodiments generally comprise a voltage generator to create a sub-threshold voltage for a memory state of memory cells in a block. Once the sub-threshold voltage is applied to a word line a state reader determines states of memory cells coupled to the word line. If the state reader determines that one or more of the memory cells coupled to the word line is in the memory state, despite the sub-threshold voltage, a memory refresher may program a number of memory cells in the block. Method embodiments generally comprise applying a sub-threshold voltage to a word line for a plurality of memory cells, detecting at least one memory cell of the plurality violates a state parameter, and refreshing a block of memory cells associated with the plurality of cells.

Methods and apparatuses for refreshing non-volatile memory

An apparatus and technique for testing of multi-level cells (MLC) in a memory storage device using a high bandwidth data path architecture. The technique includes hardware for obtaining a first data and a second data from a multilevel cell memory. The first data is different from the second data. The first data and second data are compared and, based at least in part on this comparison, the multilevel cell memory is programmed. Programming the multilevel cell memory includes accessing memory cells in the multilevel cell memory and determining the number of bits per memory cell of the first data that need programming.

High bandwidth datapath load and test of multi-level memory cells

Cells in a non-volatile memory are programmed in parallel using a variable program bandwidth. The variable program bandwidth is an automatic variation in the number of cells pulsed in parallel based upon a predefined electrical current provisioning capability. The variation in programming number may be based upon whether a program pulse represents an initial pulse or a re-pulse. Additionally, or alternatively, the variation in programming number may be based upon a cell level to be programmed by a pulse in a MLC device.

Storing data in-non-volatile memory devices

Storing data in non-volatile memory devices

Programming non-volatile memory devices includes identifying addresses in a data buffer for storing a particular one of a plurality of threshold voltage levels, then pulsing the array memory cells to program the array memory cells to the particular threshold voltage level. The identifying and pulsing is repeated for each of the threshold voltage levels.

Growing community of inventors

Cameron Park, CA, United States of America

Daniel R Elmhurst