Sun Microsystems, Inc.

Thinking Machines Corporation

Oracle America, Inc.

Daniel R Cassiday

Guy Lewis Steele, Jr

David L Satterfield

Steven K Heller

Jon P Wade

W Daniel Hillis

Charles D Binford

Mahesh N Ganmukhi

David C Douglas

John R Feehrer

Randall David Rettberg

John D Acton

Monica C Wong-Chan

Andrew W Wilson

Jeffrey V Hill

Robert C Zak, Jr

Shaw-Wen Yang

Robert D Lordi

Zahi S Abuhamdeh

Pazhani Pillai

Raymond J Lanza

Margaret A St Pierre

Thomas J Moser

Scott J Smith

Radia Joy Perlman

Drew George Doblar

Ariel Hendel

Mark Donald Hill

David Allen Wood

Christopher J Jackson

Jyh-Ming Jong

Derek Tsai

Boris Ostrovsky

Katsushi Asahina

Mistsuo Magane

Soroush Shakib

Don M Morrier

A system, methods and apparatus perform remote access commands between nodes and allow preemption of context resources in an architecture such as Infiniband. The system detects an original request in a request queue for a data access task to access data from a first node to a second node and issues a first request from a first node to a second node. The first request requests the data access task be performed between the first node and the second node. The system receives, at the first node, a first response from the second node that partially completes the data access task. The system issues at least one subsidiary request from the first node to the second node to further complete the data access task between the first node and the second node. The subsidiary request(s) are based on an amount of partial completion of the data access task between the first node and the second node. The system receives, from the second node in response to the subsidiary request, at least one corresponding subsidiary response that further completes the data access task between the first node and the second node. Reponses are limited in size to a data allotment, such that a large data access request may be broken into several smaller subsidiary data access request response sequences, thus allowing preemption of context resources in between processing of request response pairs.

Methods and apparatus for performing remote access commands between nodes

A plurality of PCIe switch complexes are interposed between a plurality of I/O devices and a plurality of microprocessor complexes. Each PCIe switching complex comprises a plurality of PCIe switches wherein each switch possesses at least one non-transparent port. The non-transparent port is used to cross-couple each PCIe switch creating an active matrix of paths between the HBAs associated with each I/O device and each microprocessor. The paths between each HBA (I/O device) and each microprocessor are mapped using a recursive algorithm providing each I/O device with direct memory access to each microprocessor.

Cross-coupled peripheral component interconnect express switch

Data buffering allocation in a microprocessor complex for a request of memory allocation is supported through a remote buffer batch allocation protocol. The separation of control and data placement allows simultaneous maximization of microprocessor complex load sharing, and minimization of inter-processor signaling/metadata migration. Separating processing control from data placement allows the location of data buffering to be chosen so as to maximize bus bandwidth utilization and achieve non-blocking switch behavior. This separation reduces the need for inter-processor communication and associated interrupts thus improving computation efficiency and performance.

Data buffer allocation in a non-blocking data services platform using input/output switching fabric

Methods and apparatus are disclosed for enabling nodes in a data network having interconnect links to continue to transmit data when a link fails. This is done in realtime, in a manner transparent to upper-level clients, and at a hardware level without software intervention. A method is described in which a data packet is received or stored in a transmitter buffer at an originating node having a failed link where the data packet is scheduled to use the failed link. The data packet is routed to a failover storage area. The failover storage area is a shared resource in the node and consists of two first-in, first-out stacks for processing and routing the failover data packets. If needed, an alternative link is selected for the data packet and the data packet is routed to a transmitter associated with the alternative link. An alternative link is selected using a primary and secondary routing table, also part of the shared resource of the node. The data packet is then transmitted to a receiver for the alternative link at a destination or multihop node. This allows the data packet to reach the remote end of a failed link by sharing alternate links connecting the local and remote ends of a failed link.

Automatic link failover in data networks

An optical transmitter for transmitting a first output data signal and a second output data signal, the optical transmitter comprising: a phase-locked-loop, the phase-locked-loop operable to receive a reference clock signal; a clock-recovery circuit, the clock-recovery circuit coupled to the phase-locked-loop, the clock-recovery circuit operable to receive a first input data signal; a latch-decision circuit, the latch-decision circuit coupled to the clock-recovery circuit; a latch, the latch coupled to the latch-decision circuit, the latch operable to receive the first input data signal and the second input data signal; a first electro-optical converter, the first electro-optical converter coupled to the latch, the first electro-optical converter operable to transmit the first output data signal; and a second electro-optical converter, the second electro-optical converter coupled to the latch, the second electro-optical converter operable to transmit the second output data signal.

Optical transmitter for transmitting a plurality of output signals

Methods and components in an interconnect system for improving the performance of the system with respect to increasing bandwidth in a serial link, increasing the processing speed of a packet in a node, and improving the calibration of links in the system are described. In one aspect of the present invention, a method of encoding framing data in a packet such that less than the normal number of framing bits is required. For example, a flit, the data unit sent over a serial link in one clock cycle, can be 88 bits in length, and a packet can be made up of one, two, or four flits. If the packet is a one- flit packet, two framing bits are inserted into the packet. If the packet is two flits, four framing bits are inserted into the packet, and if it is a four-flit packet, eight framing bits are inserted. In this way, space in the packet for data is maximized and the total number of bits of the packet can be determined either after reading a first framing bit if the packet is one flit or after reading a second framing bit if the packet is two or four flits long.

High performance transmission link and interconnect

A system and method for superimposing a sequence number of a packet into the CRC segment of the packet thereby allowing more bandwidth in the payload portion of the packet for carrying data is described. Also described is a method of acquiring additional information on the type of error in a packet, e.g., data transmission errors or sequence errors, from analyzing a CRC error. For example, a reported CRC error can be the result of the receipt of a packet with a sequence number the receiver is not expecting (which is a normal occurrence on transmission links due to transmitters resending packets that a receiver has already accepted) or can result from a real error in the transmission of a packet. A first error code check (CRC) value is calculated for the payload segment of a data packet. A second CRC value is calculated for the sequence number of the data packet. The first CRC value and the second CRC value are combined thereby creating a third CRC value. The third CRC value is then combined with the payload segment of the data packet thereby creating a data packet that can be transmitted across the link.

Method for superimposing a sequence number in an error detection code in a data network

A method and device for virtual memory support in a computer system using a mapping structure for address translation. Mapping indicators are associated with each process context and each mapping structure entry. When a context is demapped the mapping indicator associated with the context is changed and the mapping indicator in each mapping structure entry is employed to immediately invalidate further memory accesses for that context.

Method and device for a context-based memory management system

In accordance with methods and systems consistent with the present invention, an improved failure recovery system is provided that, upon detecting a failure, generates new routings for the network which (1) avoid the failure and (2) avoid deadlock. In this manner, after a failure is detected, the network remains as operational as possible while still avoiding deadlock. Thus, by using the improved failure recovery system, a network failure has a much less severe impact on the network than in conventional systems.

Dynamic generation of deadlock-free routings

A central node in a network computes for, and sends to, each node a forwarding table which consists of the set of neighbors to which the node should forward a message intended for a particular destination. The message includes a version number in the packet field header indicating which forwarding table version the node should use to forward the packet. The node does not begin marking and forwarding packets according to the new version number immediately. The node may wait a period of time after receiving the new table or may wait until receiving notification from the fabric manager to begin using the new version number. When a node receives a message from an end node, it inserts either the most recently received version number in one embodiment or uses the version dictated by the fabric manager in another embodiment. If the node receives a message from another node with a forwarding table version not resident at the node, the node will forward the packet with the most recent version of the forwarding table it has resident and change the version in the message accordingly prior to forwarding.

Coordinating loop-free forwarding table updates

System and method for rapidly calculating CRC values for messages including encoded bits is described. Tabularized CRC values are used in combination with a logical grid to quickly determine an appropriate CRC value of a message. This determination can take into account encoded inversion bits in the message. A collection of pre-calculated CRC values are arranged in a single-column table and then implemented with selected bits of a message by superimposing the bits in each CRC value onto a logical grid. Vertical lines of the grid are associated with 30 exclusive OR (XOR) gates and horizontal lines are associated with bits in an 88-bit message (or the 30 bits of a CRC value or with 8 bits of a sequence number). Through this grid, the inputs to the XOR gates are determined, thereby facilitating rapid calculations of CRC values due to the high processing speeds possible in XOR gates.

Method for detecting errors on parallel links

Methods and systems consistent with the present invention provide a family of networks ranging from 2 nodes to 16 nodes that can be partitioned in an unconstrained manner. That is, where the number of nodes in one of these networks is N, subnetwork can contain any number of nodes from 1 to N&minus;1 as long as the total number of nodes in both subnetworks equals N. Furthermore, each subnetwork can be partitioned repeatedly until reaching the atomic level (i.e., when the subnetwork contains a single node). In accordance with methods and systems consistent with the present invention, when a network is partitioned, each subnetwork has various desirable properties. For example, the maximum path length between any two nodes in each subnetwork nodes is 3, and each to subnetwork has a set of deadlock-free routings.

Recursive partitioning of networks

In accordance with methods and systems consistent with the present invention, an improved technique for reconfiguring networks is provided. By using this technique, a network administrator can reconfigure their network while it remains operational. As a result, users can continue to utilize the network during reconfiguration. Additionally, in accordance with methods and systems consistent with the present invention, a number of network topologies are provided that are designed to facilitate reconfiguration. When using one of these topologies, the network can be reconfigured with a minimal amount of recabling, thus reducing the amount of time required for reconfiguration.

Network reconfiguration

In accordance with methods and systems consistent with the present invention, an improved deadlock-free routing system is provided to a family of network topologies where both the configuration of the networks and the routings are designed to optimize performance. In this system, each network utilizes static routing tables that perform deadlock-free routing in an optimized manner to reduce the amount of communication overhead when routing traffic. Specifically, the routings in accordance with methods and systems consistent with the present invention require no more than two hops for networks up to a size of 16 nodes. As a result, the deadlock-free routing provided in accordance with methods and systems consistent with the present invention incurs less communications overhead than some conventional systems while still avoiding deadlock.

Deadlock-free routing

A massively-parallel computer includes a plurality of processing nodes and at least one control node interconnected by a network. The network faciliates the transfer of data among the processing nodes and of commands from the control node to the processing nodes. Each processing node includes an interface for transmitting data over, and receiving data and commands from, the network, at least one memory module for storing data, a node processor and an auxiliary processor. The node processor receives commands received by the interface and processes data in response thereto, in the process generating memory access requests for facilitating the retrieval of data from or storage of data in the memory module. The node processor further controlling the transfer of data over the network by the interface. The auxiliary processor is connected to the memory module and the node processor. In response to memory access requests from the node processor, the auxiliary processor performs a memory access operation to store data received from the node processor in the memory module, or to retrieve data from the memory module for transfer to the node processor. In response to auxiliary processing instructions from the node processor, the auxiliary processor performs data processing operations in connection with data in the memory module.

Growing community of inventors

Topsfield, MA, United States of America

Daniel R Cassiday