Vlsi Technology, Inc.

Daniel R Brasen

Sunil V Ashtaputre

Mark R Hartoog

Dale M Wong

James D Shiffer, Ii

Bruce S Seiler

Sunil Asktaputre

A floor-plan of component blocks of logical circuits, including the symbolic routing of major connection networks, is produced as part of the process for laying out an integrated circuit on a chip. The floor-plan is produced before performing optimized placement and routing of logical circuits within component blocks of the VLSI circuit. First, the logical circuits are apportioned into component blocks. Then, an initial lay out of the component blocks of the VLSI circuit is performed. The major connection networks are routed between the component blocks so that the major connection networks are connected to connection areas within the component blocks. The initial lay out of component blocks is adjusted as necessary in order to take into account the addition of the major connection networks. Once any needed adjustments are made, routing guidance information is generated as part of the floor plan. The routing guidance information indicates locations and sizes of the major connection networks.

Symbolic routing guidance for wire networks in VLSI circuits

Segments within a power network of an integrated circuit are calculated utilizing information generated during design and placement. The performance of logic blocks within the integrated circuit is simulated to obtain an estimated maximum current requirement for each logic block. After obtaining an estimated maximum current requirement for each logic block, the estimated maximum current flow through each power net segment is obtained by summing the estimated current requirements for each logic block which draws current through the power net segment. Based on this estimated maximum current flow through each power segment, a width for each power net segment is calculated. After widths have been calculated, a check may be made to assure that a predetermined electromigration limit is not exceeded. When projected current flow through a power net segment will result in an exceeding of the predetermined electromigration limit, the width of the power net segment is increased.

Method for sizing widths of power busses in integrated circuits

Flexible routing of gate arrays increases routing efficiency, provides for the routing of functional blocks with other gates in the gate array, and provides structures for flexible power routing, particularly of gate arrays having functional blocks. In particular, a gate-array-implemented integrated circuit is designed using a computer by representing in computer memory a gate array base, placing gate array cells on the gate array base in placement rows each having a uniform height and separated by routing channels in which no gate array cells are placed, and routing in the routing channel connections between placement rows according to a netlist, during routing increasing the size of a routing channel if required and decreasing the size of a routing channel if possible by changing the placement of at least one placement row by an amount less than half the height of the placement row. Routing channel size is therefore flexibly adjusted 'on-the-fly' during routing, increasing routing efficiency. The adjustment of routing channels in small (5 track) increments is made possible by defining 'tall' macros (four transistor rows high) made of 'small' (5 track high) transistors.

Gate array bases with flexible routing

A method performs global routing of a power line network and a ground line network on an integrated circuit. Pre-formed segments of the ground line network are placed adjacent to functional blocks of the integrated circuit. Ground lines of the functional blocks are connected to the pre-formed segments of the ground line network. In addition, pre-formed segments of the power line network are placed adjacent to the functional blocks of the integrated circuit. Power lines of the functional blocks are connected to the pre-formed segments of the power line network. Once the pre-formed segments have all been placed, the pre-formed segments of the ground line network are connected together and the pre-formed segments of the power line network are connected together.

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San Francisco, CA, United States of America

Daniel R Brasen